Electrical Engineering

VLSI critical area analysis via Voronoi diagrams
The Voronoi diagram of polygonal objects in the plane is a powerful mathematical object that encodes proximity information in a compact form. Critical Area is a widely accepted measure that reflects the sensitivity of a VLSI design to random manufacturing defects, used to predict yield. We have developed a new Design Automation tool that, based on the geometric concept of Voronoi diagrams, extracts fast and accurately the critical area of a VLSI design for all types of random manufacturing defects.

Print verification system
A Print Verification System scans and processes printed pages in real time to verify their print quality. Verifying pages printed at more than 750 per minute, it replaces previous manual inspection of randomly selected pages and thus reduces operational cost and delivers more consistent results.

Fast quasi-static capacitance extraction using CSurf
The Electrical Interconnect and Packaging (EIP) group provides best-of-breed electrical designs, modeling and simulation tools, as well as characterization techniques for new products and future packaging needs in supercomputers and servers. One of the recent additions to this suite of electromagnetic (EM) modeling tools is an arbitrary shape 3D solver named Csurf, which stands for quasi-static capacitance extraction based on surface integral equation (or boundary element method). Benchmarks have demonstrated that Csurf can out-perform Ansoft Q3D by over 100 times for via array structures in multilayer dielectrics.