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| Computer Design in the Nanometer Scale Era: Challenges and Solutions | ||||
| David Brooks | On: | 11-Jul-2008 10:00 AM - 11:30 AM | ||
| Harvard University | At: | Watson Research Center (Yorktown), Room 20-001 | ||
Abstract: Technology scaling has enabled tremendous growth in the computing industry over the past few decades. However, recent trends in power dissipation, reliability, thermal constraints, and device variability threaten to limit the continued benefits of device scaling, curtail performance improvements, and cause increased leakage power in future technology generations. The temporal and spatial scales of these effects motivate holistic solutions that span the circuit, architecture, and software layers. In this talk, I will describe several ongoing projects that seek to address technology scaling issues. The talk will also discuss our chip prototyping efforts that support this work. | ||||
Past seminars
| Dynamic Synthesis: Shrink-Wrapping Hardware to Fit Software | ||||
| Doug Burger | On: | 11-Apr-2008 10:00 AM - 11:30 AM | ||
| Assoc. professor | At: | Watson Research Center (Yorktown), Room 20-001 | ||
| University of Texas at Austin | ||||
Abstract: While CMP hardware is becoming prevalent, outside of the server domain it is unclear whether this hardware will provide sufficient performance, programmability, or power efficiency. In this talk, I will present a new concept called Dynamic Synthesis, in which virtual processors are built out of many discrete, lightweight networked components on chip, with the goal of precisely meeting the needs of the software. With this approach, the cache sizes, issue width, window size, and number of cores can all be adjusted based on workload mix, power constraints, and application phases to achieve better performance and/or higher efficiencies. While the current design is limited to EDGE architectures, it is my hope that the concepts can be eventually retrofitted onto conventional designs. Speaker biography: Doug Burger is an Associate Professor of Computer Sciences at the University of Texas at Austin. He received his B.S. in Computer Science from Yale University, and his M.S. and Ph.D. from the University of Wisconsin-Madison. He is known for his work on the SimpleScalar Tool Suite, for co-designing the TRIPS architecture, and for his work on technology scalable architectures, including NUCA caches, for which he received the ACM Maurice Wilkes Award in 2006. In May, he starts work as the Research Area Manager for Computer Architecture at Microsoft Research, with an affiliate professorship at the University of Washington. He is a Senior Member of IEEE and ACM, and is Chair of ACM SIGARCH. | ||||
| 3D Integration for High-Performance Processor Microarchitectures | ||||
| Gabriel Loh | On: | 10-Mar-2008 10:00 AM - 11:30 AM | ||
| Assistant Professor | At: | Watson Research Center (Yorktown), Room 20-001 | ||
| Georgia Institute of Technology | ||||
Abstract: Three-dimensional integration is a new fabrication technology that allows stacking multiple layers of silicon into a single, tightly integrated system. The advantages include greater device density, drastic reduction in wiring due to the flexibility of 3D placement and routing, and the potential for integration of heterogeneous technologies. In this talk, I will present some of the 3D microarchitecture work happening at Georgia Tech which includes several applications of 3D at different levels of granularity: at the circuit level, functional unit block level, and at the system level. Speaker biography: Gabriel H. Loh received the B.E. degree in electrical engineering from Cooper Union, New York, NY, in 1998, and the M.S. and Ph.D. degrees in computer science from Yale University, New Haven, CT, in 1999 and 2002, respectively. From 2003 to 2004, he was a Senior Researcher with the Microarchitecture Research Laboratory at Intel Corporation. He is currently an Assistant Professor in the School of Computer Science at the Georgia Institute of Technology. His research interests include computer architecture, processor microarchitecture, simulation, circuit design, three-dimensional integration technology, and ice hockey. He is a recipient of the NSF faculty early career development (CAREER) award. | ||||
| Emerging Issues for Next-Generation Microprocessors | ||||
| Margaret Martonosi | On: | 25-Feb-2008 10:00 AM - 11:30 AM | ||
| Professor of Electrical Engineering | At: | Watson Research Center (Yorktown), Room 20-043 | ||
| Princeton University | ||||
Abstract: In a surprisingly short period of time, Moore's Law has brought about important shifts in computer architecture. The default processor has become multicore, and issues like power-efficiency, and variation-tolerance are being viewed on par with performance when addressing design priorities. I will discuss some of my group's recent research in these areas, with a particular focus on (i) architectural support for lightweight parallelism, (ii) strategies for variation tolerance, and (iii) FPGA-based emulation approaches that accelerate architectural evaluations. | ||||
| Attack of the Killer Game Machines | ||||
| Sanjay Patel | On: | 9-Nov-2007 10:00 AM - 11:30 AM | ||
| University Of Illinios (Urbana-Champaign) | At: | Watson Research Center (Yorktown), Room 20-001 | ||
Abstract: In early 2005, AGEIA introduced the notion of an accelerator card for physical simulation of video games. Since then, there has been a rush of activity from several major semiconductor vendors to jump onto the physics bandwagon. This is another example of how the semiconductor economy is responding to the "data scale" world, driven by the video games at its base, and extending into a broadening high- performance computing market. The implications for processor architecture are monumental. Physics is a good example of a data scale workload, and in this talk we'll examine the interesting challenges of designing solutions for the interactive physics space. We'll take a deep dive into the architecture of the AGEIA PhysX chip, and examine the forces that are driving the evolution of the AGEIA PhysX Architecture. The evolution of the AGEIA architecture is embodied the Rigel Project, which is an accelerator architecture my colleagues and I are developing at UIUC. Speaker biography: Sanjay J. Patel is an Associate Professor of Electrical and Computer Engineering and Willett Faculty Scholar at the University of Illinois at Urbana-Champaign, where he pursues his research interest in designing ultra high-performance architectures. Since 2004, Sanjay has been the Chief Architect at AGEIA Technologies, overseeing the architecture and design of AGEIA's high- performance ASICs for accelerating physical simulation in video games. He is the co-author (with Yale Patt of The University of Texas at Austin) of an introductory textbook for computer science and engineering students, titled "Introduction to Computing Systems: From Bits and Gates to C and Beyond", which is now available in its second edition from McGraw-Hill. Patel earned his Bachelor (1990), Master of Science (1992) and PhD (1999) in Computer Science and Engineering from the University of Michigan, Ann Arbor. | ||||
| Orchestrating the Execution of Streaming Applications on Multicore Platforms | ||||
| Scott Mahlke | On: | 1-Nov-2007 03:30 PM - 04:30 PM | ||
| University Of Michigan | At: | Watson Research Center (Yorktown), Room 20-043 | ||
Abstract: While multicore hardware has become ubiquitous, explicit parallel programming models and compiler techniques for exploiting parallelism on these systems have noticeably lagged behind. Stream programming is one model that has wide applicability in the multimedia, graphics, and signal processing domains. Streaming models execution as a set of independent actors that explicitly communicate data through channels. While stream programs contain an abundance of parallelism, the central challenge is efficiently mapping the applications across multiple processors. Compilers must account for communication overhead as well as resource and memory limitations to generate efficient mappings. This talk will describe the StreamRoller compilation system that plans and orchestrates the execution of streaming applications on decoupled multicore platforms. The compiler packs computation onto cores jointly considering load balance along with resource, dependence, and communication constraints. We have developed a generalized code generation template for mapping the resultant schedules onto existing multicore systems, including the Cell architecture. Using fully automated techniques, StreamRoller achieves an average speedup of 5.2x on an 8-core Cell compared to a single core for a range of streaming applications. | ||||
| Microprocessor Performance, Phase 2: Can We Harness the Transformation Hierarchy? | ||||
| Yale Patt | On: | 19-Oct-2007 10:00 AM - 11:30 AM | ||
| Professsor | At: | Watson Research Center (Yorktown), Room 20-043 | ||
| University Of Texas, Austin | ||||
Abstract: We see a major change lately in the way we harness the fruits of process technology. With more than one billion transistors on a chip today, and 100 billion in a few years, and frequencies already in the gigahertz range and increasing as well, the current thrust is toward chip multiprocessors and worrying about power and energy. But these are not without problems. I submit that this continued growth in on-chip capability has pushed us into Phase 2 of our quest for continued microprocessor performance, and things will have to be different. In this talk, I will characterize what I think the difference is between phase 1 and phase 2, what we need to do differently in phase 2, and what I see as the most important impediment to accommplishing it. Speaker biography: Yale Patt is a professor of electrical engineering and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He has received a number of awards for his research and teaching, most notably the 1996 IEEE/ACM Eckert-Mauchly Award, and the 2000 ACM Karl V. Karlstrom Outstanding Educator Award. | ||||
| Automatic Thread Extraction for Notoriously Sequential Programs | ||||
| David August | On: | 11-Jul-2007 10:00 AM - 11:30 AM | ||
| Associate Professor, Department of Computer Science | At: | Watson Research Center (Yorktown), Room 20-001 | ||
| Princeton University | ||||
Abstract: For years, a steadily growing clock rate could be relied upon to consistently deliver increasing performance for a wide range of applications. Recently, however, this approach has faltered. Meanwhile, the exponential growth in per-chip transistor count remains strong, leading microprocessor companies to add value by producing chips incorporating multiple processors. Unfortunately, since decades of compiler research have not succeeded in delivering automatic thread extraction for ordinary sequential codes, current chip multiprocessing produces no improvement for most applications. Our examination of program dependence graphs in the context of multiple core processors led us to develop several new techniques for automatic thread extraction. Building on this perspective, our examination of popular sequential programming models led us to develop an easy to use and natural extension to alleviating their limitations. These developments produce a more than 5x performance improvement (when limited to 32 cores) on the notoriously sequential SPEC C INT 2000 benchmark programs when building on the modification of only 56 lines of code across the entire benchmark suite. As a result, we have found a concrete path to drastically reducing the cost of programming the multiple core devices coming from industry, a path requiring minimal programmer intervention to continue the historic "Moore's Law of Performance" trend for at least 5 more generations. Speaker biography: David I. August is an Associate Professor in the Department of Computer Science at Princeton University. At Princeton, he directs the Liberty Research Group (http://liberty.princeton.edu). The Liberty Research Group is studying next generation architectures, code analyses, and code transformations to enhance performance, reliability, and security. David's work has been recognized by an NSF CAREER Award, an Emerson Electric Company - E. Lawrence Keyes '51 Award, an IBM Faculty Partnership Award, several best paper awards, and The Chronicle of Higher Education's annual list of "New Ph.D.'s to Watch". David earned his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign in 2000 while working as a member of the IMPACT research group. | ||||