Over the years, IBM Research has made seminal contributions to the field of computer architecture. The IBM System/360 model 91, contained basic ideas for out-of-order issue high-performance processors. Pioneering work on Reduced Instruction Set Computer (RISC) architectures and compilers, inspired by the ideas of the late IBM visionary John Cocke was done at IBM Research as part of the 801 Minicomputer project. The Yorktown Simulation Engine was an example of a highly parallel computer for gate-level logic simulation. Other supercomputers conceived and built at IBM Research include the GF11, which made a long and massive numerical calculation to help solve a quantum chromodynamics problem, and the RP3 Parallel Processor, which was a highly parallel multiprocessor with a special switch to reduce memory contention.
Supercomputing Architecture Research
One of the most exciting examples of highly parallel computing research was IBM's Deep Blue parallel computer, which beat the human world chess champion in 1997. Now, the parallel computing technology of Deep Blue is being applied to other areas. Recently, we also contributed to the ASCI White and Blue Pacific supercomputers, which are a part of the U.S. government's high-performance Accelerated Strategic Computing Initiative (ASCI).
With the Blue Gene project, IBM is pushing against the ultimate technological boundaries of performance. Blue Gene aims to tackle the protein-folding Grand Challenge problem with a performance of 1 petaflop (approximately 1015operations per second).
High-Performance Microprocessor Design
The fields of instruction level parallelism and microarchitecture form the basis of our technical activities in high-performance microprocessor research. DAISY (Dynamically Architected Instruction Set) developed at Watson Research Center is an open-source project that aims to use binary translation to achieve 100 percent architectural compatibility with existing processors (for example, PowerPC®, S/390®, Java™ VM) on a wide issue VLIW (Very Long Instruction Word) engine. The MET (Microarchitecture Exploration Toolset) project addresses the exploration of options and simulation tools in the design of PowerPC processors. Our VLIW research project resulted in a hardware prototype and three generations of compilers. Our efforts in memory systems microarchitecture and timers have contributed to IBM's commercial processors, with the associated inventions being used throughout the industry. We are also engaged in very high-frequency microprocessor design , aimed at constructing multi-GHz processor chips.
Digital Signal Processors
The world is not only demanding fast systems, it is also depending on small wireless systems. Digital signal processors (DSPs) are accelerating this trend. DSPs have become an ubiquitous enabler for the integration of audio, video, and communications. We are researching an ultralow-power DSP/embedded processor , capable of meeting the performance requirements of the new generation of wireless standards, while consuming only a few milliwatts of power when implemented in IBM's next generation 0.13-micron CMOS technology. An important component of this research is the associated optimizing compiler being developed in conjunction with the architecture, which makes possible program development using the C language while achieving performance comparable to assembly language without the use of custom libraries. Our unique research focus areas in DSPs include new circuit techniques for ultralow-power compiler optimizations for DSP operations, architectures and microarchitectures optimized for low-power, and system-level design experience.
Related Publications
B. Abali, M. Banikazemi, X. W. Shen, H. Franke, D. E. Poff and T. B. Smith. Hardware Compressed Main Memory: Operating System Support and Performance. IEEE Transactions on Computers 50(11), November 2001.
Kemal Ebcioglu, Erik Altman, Michael Gschwind and Sumedh Sathaye. Dynamic Binary Translation and Optimization. IEEE Transactions on Computers 50(6):529-548, June 2001. [ download ]
Allan M. Hartstein and Thomas R. Puzak. The Optimum Pipeline Depth for a Microprocessor. Proceedings of 29th Annual International Symposium on Computer Architecture, Anchorage, Alaska. June 2002.
Allan M. Hartstein and Thomas R. Puzak. OPTIMUM POWER/PERFORMANCE PIPELINE DEPTH. Micro 2003 - 36th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE / ACM, December 2003.
Recent Accomplishments
Jaime Moreno, general co-chair, CASES 2003, San Jose, CA, October 2003
Vivek Sarkar, program co-chair, PACT 2003, New Orleans, LA, September 2003.
Kemal Ebcioglu, general chair, MICRO-35, Istanbul, Turkey, November 2002
Erik Altman, program co-chair, PACT 2002, Charlottesville, VA, September 2002.
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