The rapidly growing complexity of designs makes late design changes increasingly expensive. In order to prevent late changes, design trade-offs need to be evaluated as early as possible in the design cycle. To enable this early analysis we have developed SLATE (System-Level Analysis Tool for early Exploration), an environment that integrates performance, power, thermal and interconnect models at the transaction level of abstraction, based an a SystemC simulator and floorplan data (see Fig. 1). SLATE guides the designer in understanding the implications of the trade-offs, it supports decision making and drives the resulting implementation process.
To demonstrate the value of the SLATE approach, we have applied it to the exploration of power management algorithms for multi-core systems (see Fig. 2). Power consumption and heat dissipation of systems have become a major design concern. They can be traded off against performance to meet a given power budget, and this trade-off can be optimized dynamically by power-management algorithms to maximize performance for a given power budget. Multi-core, multi-threaded systems in particular offer a large design space for this optimization.
As an example, we used SLATE to build a model of a system with four processor cores and level-2 caches, a bus, and a memory controller. This system also includes a power management unit (ChipPM in Figure 2) which implements the power management algorithms and decides, in regular intervals, which voltage and frequency to apply to each core in the design. Different algorithms can be easily plugged into the SLATE infrastructure to compare the resulting power and performance (Fig. 3). The approach enabled us to quickly develop a variety of power management algorithms, with SLATE providing guidance towards the best candidates.
Publications
1. Exploring Power Management in Multi-Core Systems (pdf), Reinaldo Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren Patel, Indira Nair, Geert Janssen, Gero Dittmann, Nagu Dhanwada, Zhigang Hu, Pradip Bose, John Darringer, in Proceedings of the 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008), Seoul, Korea, January 2008.
2. Performance Modeling for Early Analysis of Multi-Core Systems," Reinaldo Bergamaschi, Indira Nair, Gero Dittmann, Hiren Patel, Geert Janssen, Nagu Dhanwada, Alper Buyuktosunoglu, Emrah Acer, Gi-Joon Nam, Guoling Han, Dorothy Kucar, Pradip Bose, and John Darringer, in Proceedings of CODES+ISSS 2007, Sept. 30-Oct. 5, 2007.
3. "A Power Estimation Methodology for SystemC Transaction-Level Models," N. Dhanwada, I.-C. Lin, V. Narayanan, in Proceedings of the Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2005), Sept. 18-23, 2005, pp.142-147.
4. "SEAS: A System for Early Analysis of SoCs," R. Bergamaschi, Y. Shin, N. Dhanwada, S. Bhattacharya, W. Dougherty, I. Nair, J. Darringer, S. Paliwal, in Proceedings of the First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2003), Oct. 1-3, 2003, pp.150-155.
5. "Early Analysis Tools for System-on-a-Chip Design" (pdf), J. Darringer, R. Bergamaschi, S. Bhattacharya, D. Brand, A. Herkersdorf, J. Morrell, I. Nair, P. Sagmeister, Y. Shin, in IBM Journal of Research and Development, Vol.46, No.6, Nov. 2001, pp.691-707.
6. "Automating the Design of Systems-on-Chip Using Cores," R. Bergamaschi, S. Bhattacharya, R. Wagner, C. Fellenz, M. Muhlada, W. Lee, F. White and J.-M. Daveau, in IEEE Design & Test Magazine, Vo.18, No. 5, Sept. 2001, pp.32-45.
Last updated May 19, 2008