Austin Research Lab (ARL)
The IBM Austin Research Laboratory is one of eight IBM research laboratories worldwide. The lab's original focus centered heavily on high-speed microprocessors, with emphasis on very fast circuit families and computer-aided design tools to support complex and high performance microarchitectures. The ARL has not only maintained its edge in these areas, but broadened its concentration to include software and hardware systems.
Current focus areas of ARL include high performance/low power VLSI design and tools, system-level power analysis, and new system architectures. There is a wide range of low power and energy efficiency activities underway throughout the multiple IBM Research laboratories and throughout the various IBM product and services divisions.
In addition to its own ongoing power-related research, ARL, as part of IBM's Low Power Initiative, is helping to coordinate low power and energy efficiency activities and bring people together throughout IBM who are working in these important areas. ARL also organizes and hosts the Austin Conference on Energy-Efficient Design (ACEED).
Thomas J. Watson Research Center
At the Thomas J. Watson Research Center, other groups focus on related problems. Included are circuit and technology co-design, whose goal is to establish an early circuit design infrastructure and assess the performance leverage of such devices, and understand any significant issues arising from their use, and circuit-architecture co-design concepts, initially examining ways to turn off unused parts of a processor in a way that has minimal impact on performance.
Reserachers are also involved in actual designs of processors for products, including high-performance microprocessors in mainframe and server products and the "Cell" microprocessor (a joint development effort among SCEI, Toshiba, and IBM) where the Watson team is contributing in leadership roles, circuit deliverables, and tools methodology, using its experience from earlier designs to leverage the design of this new scalable chip architecture, providing innovations at the circuit and logic level to produce high performance designs in time for product use. These design activities also provide the community with an intimate knowledge of the issues that must be addressed in order to meet the continuous need for increased performance, and also provide an outstanding test environment for new design tools and methodologies.
Related Publications
Ching-Te Chuang and Ruchir Puri. Effects of Gate-to-Body Tunneling Current on PD/SOI CMOS Latches. 2003 International Conf. on Simulation of Semiconductor Processes and Devices : SISPAD2003. IEEE Electron Device Society, September 2003.
Arvind Kumar, Massimo V. Fischetti, Tak H. Ning and Evgeni Gousev. Hot-Carrier Charge Trapping and Trap Generation in HfO2 and Al2O3 Field-Effect Transistors. Journal of Applied Physics 94(3):1728-37, August 2003.
K. Nowka, et.al., "A 32-bit PowerPC System-on-a-Chip With Support for Dynamic Voltage Scaling abd Dynamic Frequency Scaling", IEEE Journal of Solid State Circuits, Vol. 37, No. 11, pp. 1441-7.
Mary Y. Wisniewski et. al., "The Physical Design of on-Chip Interconnections", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 3, pp. 254-276.
V. Srinivasan, et.al. "Optimizing Pipelines for Power and Performance" Proceedings of the 35th Annual IEEE/ACM International Symposium on Mircoarchitecture, pp 333-44.
Recent Accomplishments
Azeez Bhavnagarwala - Member of the Technical Program Committee for the 2003 IEEE International ASIC Conference and the International Conference on Computer Design.
Stephen Kosonocky - Member of the Technical Program Committee for the International Solid State Circuits Conference (2/2003).
William Reohr - Chairman of the Industrial Advisory Board for the Microelectronics Design Center, serving from 10/2002 to 10/2004.
Stanley Schuster and Peter Cook - Presented an invited talk ("Low Power Locally Asynchronous Interlocked Pipelined CMOS Circuits Operating at 3.3-4.5 GHz") at the International Symposium on Computer Architecture (5/2002).
James Warnock - Member of the Program Committee for the International Solid State Circuits Conference, and has been invited to give a talk ("Circuit Design Issues for the Power4 Chip") at the 2003 International Symposium on VLSI Technology, Systems and Applications.
Mary Wisniewski - Member of the Board of Governors of the IEEE Lasers and Electro-Optics Society (LEOS), serving from 1/2003 to 12/2006. She is also the IEEE-LEOS Newsletter representative to the IEEE Technical Advisory Board. She presented an invited talk ("The Physics of Computer Components") at the 88th New York State Section APS/Association of Physics Teachers Semi-Annual Symposium (4,2003), and is a symposium organizer for the Special Symposium on Lasers end Electro-Optics in Semiconductor Testing at the IEEE-LEOS Annual Meeting (10/2003).
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A"typical" VLSI chip