Publication and bibtex entries are available here, or using the links below.
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- Using advanced compiler technology to exploit the performance of the Cell Broadband Engine (TM) architecture (link)
- IBM System Journal, Vol 45, Num 1, 2006. (with J. K. O'Brien, K. M. O'Brien, P. Wu, T. Chen, P. H. Oden, D. A. Prener, J. C. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang, P. Zhao, M. K. Gschwind, R. Archambault, Y. Gao, and R. Koo)
Optimizing Compiler for the CELL Processor- PACT 2005. (with K. O'Brien, K. O'Brien, P. Wu, T. Chen, P. Oden, D. Prener, J. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang, P. Zhao, and M. Gschwind)
- Efficient SIMD Code Generation for Runtime Alignment and Length Conversion
- CGO 2005. (with P. Wu, A. Wang)
- An Integrated Simdization Framework Using Virtual Vectors
- ICS 2005. (with P. Wu, A. Wang, P. Zhao)
- Vectorization for SIMD architectures with alignment constraints
- PLDI, 2004. (With P. Wu, K. O'Brien)
- An Experimental Study of Algorithms for Weighted Completion Time Scheduling
- Algorithmica 33(1): 34-51, 2002. (With I. Baev, W. Meleis)
- Scheduling Superblocks with Bound-Based Branch Trade-Offs
- IEEE Trans. Computers 50(8): 784-797, 2001. (With I. Baev, W. Meleis)
- Lower bounds on precedence-constrained scheduling for parallel processors
- Inf. Process. Lett. 83(1): 27-32, 2002. (With I. Baev, W. Meleis)
- An integrated approach to accelerate data and predicate computations in hyperblocks
- MICRO 2000. (With W. Meleis, S. Maradani)
- Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
- MICRO 1999. (With W. Meleis)
- Efficient Edge Profiling for ILP-Processors.
- PACT 1998 (with S. Lobo).
- Effective Cluster Assignment for Modulo Scheduling
- MICRO 1998. (With E. Nystrom).
- Efficient Formulation for Optimal Modulo Schedulers
- PLDI 1997. (With E.S. Davidson)
- A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints
- PLDI 1996. (With E.S. Davidson)
- Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Sched.
- International Journal of Parallel Programming, Vol 2 (2), 1996.
- (with E.S. Davidson, S.G. Abraham)
- Register Allocation for Predicated Code
- MICRO 1995. (With E.S. Davidson)
- Stage Scheduling: A Technique to Reduce the Register Requirements of a Modulo Scheduling
- MICRO 1995. (With E.S. Davidson)
- Impact of Load Imbalance on the Design of Software Barriers
- ICPP 1995 (with S.G. Abraham)
- Optimum Modulo Schedules for Minimum Register Requirements
- ICS 1995 (with E.S. Davidson, S.G. Abraham)
- Minimum Register Requirements for a Modulo Schedule
- MICRO 1994 (with E.S. Davidson, S.G. Abraham)
- Parallel Molecular Dynamics on a Multi Signalprocessor System
- Computer Physics Communications, Vol 75 (1-2),1993 (W. Scott et al.)
PLDI is the Conference on Programming Language Design and Implementation; MICRO is the International Symposium on Microarchitecture; ICS is the International Conference on Supercomputing; PACT is the International Conference on Parallel Architectures and Compilation Techniques; CGO is the International Symposium on Code Generation and Optimization; ICPP is the International Conference on Parallel Processing.
IEEE - Copyright © 1990-2001 by IEEE. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee.
ACM - Copyright © 1990-2001 by Association for Computing Machinery, Inc. Permission to make digital or hard copies of part of all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee.