Publications

Journals - Book Chapters - Conferences - Workshops

  • C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, M. Valero. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2009.
  • A. Lungu, P. Bose, A. Buyuktosunoglu, D. Sorin. Dynamic Power Gating with Quality Guarantees. International Symposium on Low Power Electronics and Design (ISLPED), August 2009.
  • C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, M. Valero. CPU Accounting in CMP Processors. IEEE Computer Architecture Letters, vol. 8, April 2009.
  • C. Boneti, F. Cazorla, R. Gioiosa, M. Valero, A. Buyuktosunoglu, C. Cher. Software-Controlled Priority Characterization of POWER5 Processor. International Symposium on Computer Architecture (ISCA), June 2008.
  • R. Bergamaschi, G. Han, A. Buyuktosunoglu, H. Patel, I. Nair, G. Janssen, G. Dittman, N. Dhanwada, Z. Hu, P. Bose, J. Darringer. Exploring Power Management in Multi-Core Systems. Asia and South Pacific Design Automation Conference (ASP-DAC), January 2008.
  • R. Bergamaschi, I. Nair, G. Dittmann, H. Patel, G. Janssen, N. Dhanwada, A. Buyuktosunoglu, E. Acar, G. Nam, G. Han, D. Kucar, P. Bose, J. Darringer. Performance Modeling for Early Analysis of Multi-core Systems. Invited Paper. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2007.
  • R. Sarikaya, A. Buyuktosunoglu. Predicting Program Behavior Based on Objective Function Minimization. International Symposium on Workload Characterization (IISWC), September 2007.
  • J. Sharkey, A. Buyuktosunoglu, P. Bose. Evaluating Design Tradeoffs in On-Chip Power Management for CMPs. International Symposium on Low Power Electronics and Design (ISLPED), August 2007.
  • C. Isci, A. Buyuktosunoglu, C. Cher, P. Bose, M. Martonosi. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. 39th International Symposium on Microarchitecture (MICRO), December 2006.
  • E. Kursun, C. Cher, A. Buyuktosunoglu, P. Bose. Investigating the Effects of Task Scheduling on Thermal Behavior. Workshop on Temperature-Aware Computer Systems (TACS), in conjunction with ISCA, June 2006.
  • C. Isci, M. Martonosi, A. Buyuktosunoglu. Long-Term Workload Phases: Duration Predictions and Applications to DVFS. IEEE Micro, September/October 2005.
  • Y. Zhu, D. H. Albonesi, A. Buyuktosunoglu. A High Performance, Energy Efficient GALS Processor Microarchitecture with Reduced Implementation Complexity. International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2005.
  • H. Jacobson, P. Bose, Z. Hu, A. Buyuktosunoglu, V. Zyuban, R. Eickemeyer, L. Eisen, J. Griswell, D. Logan, B. Sinharoy, J. Tendler. Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. High-Performance Computer Architecture (HPCA) Industrial Perspectives on Challenges for Next-Generation Computer Systems, February 2005.
  • R. Balasubramonian, V. Srinivasan, S. Dwarkadas, A. Buyuktosunoglu. Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. Springer-Verlag Lecture Notes in Computer Science Volume 3164, December 2004.
  • Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, P. Bose, H. Jacobson. Microarchitectural Techniques for Power Gating of Execution Units. International Symposium on Low Power Electronics and Design (ISLPED), August 2004.
  • D. H. Albonesi, R. Balasubramonian, S. Dropsho, S. Dwarkadas, E. G. Friedman, M. Huang, V. Kursun, G. Magklis, M. L. Scott, G. Semeraro, P. Bose, A. Buyuktosunoglu, P. W. Cook, S. E. Schuster. Adaptive Processing: Dynamically Tuning Processor Resources for Energy Efficiency. IEEE Computer, December 2003.
  • R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, S. Dwarkadas. A Dynamically Tunable Memory Hierarchy. IEEE Transactions on Computers, Vol 52, No 10, October 2003.
  • A. Buyuktosunoglu, D. H. Albonesi, T. Karkhanis, P. Bose. Energy Efficient Co-Adaptive Instruction Fetch and Issue. 30th Annual International Symposium on Computer Architecture (ISCA), June 2003.
  • P. Bose, D. Brooks, A. Buyuktosunoglu, P. W. Cook, K. Das, P. Emma, M. Gschwind, H. Jacobson, T. Karkhanis, P. Kudva, S. E. Schuster, J. Smith, V. Srinivasan, V. Zyuban, D. H. Albonesi, S. Dwarkadas. Early-Stage Definition of LPX : a Low Power Issue-Execute Processor. Power-Aware Computer Systems, Springer-Verlag Lecture Notes in Computer Science Volume 2325, May 2003.
  • A. Buyuktosunoglu, D. H. Albonesi, S. E. Schuster, D. Brooks, P. Bose, P. W. Cook. Power-Efficient Issue Queue Design. Power Aware Computing, R. Graybill and R. Melhem (Eds), Kluwer Academic Publishers, Chapter 3, pp. 37-60, 2002.
  • B. Curran, M. Gifaldi, J. Martin, A. Buyuktosunoglu, M. Margala, D. H. Albonesi. Low-Voltage 0.25um CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. SOC Design Methodologies, M. Robert, B. Rouzeyre, C. Piguet, and M. L. Flottes (Eds), Kluwer Academic Publishers, pp. 289-300, 2002.
  • S. Dropsho, A. Buyuktosunoglu, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas, G. Semeraro, G. Magklis, M. Scott. Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. 11th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2002.
  • A. Buyuktosunoglu, A. El-Moursy, D. H. Albonesi. An Oldest-First Selection Logic Implementation for Non-Compacting Issue Queues. 15th Annual International ASIC/SOC Conference, September 2002.
  • A. Buyuktosunoglu, D. H. Albonesi, P. Bose, P. W. Cook, S. E. Schuster. Tradeoffs in Power-Efficient Issue Queue Design. International Symposium on Low Power Electronics and Design (ISLPED), August 2002.
  • A. Buyuktosunoglu, S. E. Schuster, D. Brooks, P. Bose, P. W. Cook, D. H. Albonesi. An Adaptive Issue Queue for Reduced Power at High Performance. Power Aware Computer Systems, Springer-Verlag Lecture Notes in Computer Science Volume 2008, May 2001.
  • A. Buyuktosunoglu, S. E. Schuster, D. Brooks, P. Bose, P. W. Cook, D. H. Albonesi. A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors. 11th Great Lakes Symposium on VLSI (GLSVLSI), March 2001.
  • R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. 33rd International Symposium on Microarchitecture (MICRO), December 2000.
  • D. Brooks, P. Bose, S. E. Schuster, H. Jacobson, P. Kudva, A. Buyuktosunoglu, J. Wellman, V. Zyuban, M. Gupta, P. W. Cook. Power Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro, November/December 2000.
  • R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, S. Dwarkadas. Dynamic Memory Hierarchy Performance Optimization. Workshop on Solving the Memory Wall Problem, in conjunction with ISCA, June 2000.

Patents

  • Methods for Thermal Management of Three-Dimensional Integrated Circuits, with P. Bose, E. Kursun, number 7,487,012, issued 2/3/2009
  • Cost-Conscious Pre-Emptive Cache Line Displacement and Relocation Mechanisms, with Z. Hu, J. Rivers, J. Robinson, X. Shen, V. Srinivasan, number 7,454,573, issued 11/18/2008
  • Arrangements for Reducing Latency and Snooping Cost in Non-Uniform Cache Memory Architectures, with Z. Hu, J. Rivers, J. Robinson, X. Shen, V. Srinivasan, number CN ZL200610005935.4, issued 11/5/2008
  • Systems and Methods for Mutually Exclusive Activation of Microprocessor Resources to Control Maximum Power, with P. Bose, Z. Hu, H. Jacobson, V. Srinivasan, V. Zyuban, number 7,447,923, issued 11/4/2008
  • Method and System for Controlling Power in a Chip through a Power-Performance Monitor and Control Unit, with P. Bose, C. Cher, P. Kudva, number 7,421,601, issued 9/02/2008
  • Adaptive Fetch Gating in Multithreaded Processors, Fetch Control and Method of Controlling Fetches, with P. Bose, R. Eickemeyer, L. Eisen, P. Emma, J. Griswell, Z. Hu, H. Le, D. Logan, B. Sinharoy, number 7,392,366, issued 6/24/2008
  • Apparatus and Method for Dynamic Control of Double Gate Devices, with O. Dokumaci, number 7,170,772, issued 1/30/2007
  • Method and Structure for Short Range Leakage Control in Pipelined Circuits, with H. Jacobson, P. Bose, P. Cook, P. Emma, P. Kudva, S. Schuster,number 6,946,869, issued 9/20/2005
  • Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, with D. Albonesi, R. Balasubramonian, S. Dwarkadas, number 6,834,328, issued 12/21/2004
  • Dynamically Reconfigurable Memory Hierarchy, with D. Albonesi, R. Balasubramonian, S. Dwarkadas, number 6,684,298, issued 1/27/2004


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