About me
Postdoctoral Researcher
Research lab: Tokyo Research Lab
I am with the System Simulation group at the IBM Tokyo Research Laboratory developing a parallelizing compiler for synchronous dataflow languages. I am working on novel compilation techniques to exploit instruction level, data level, and thread level parallelism in closed loop control applications. My primary goal is to "bend" the causal relationships in synchronous systems to unleash parallelism suitable for high performance computing.
I received a Dr.Eng degree in computer engineering at the University of Electro-Communications of Japan in 2008. My doctoral research was focused in solving the unique compilation problems for queue machines, and I contributed with the first queue compiler prototype. Queue machines are the "parallel" siblings of stack-based architectures.
Interests: Optimizing compilers, computer architecture, high performance computing, parallel simulation
Last updated 11 Sep 2009