Chandu Visweswariah

About me

Chandu Visweswariah

Research Staff Member and Manager, Circuit and Interconnect Analysis


Research lab: Watson Research Center (Yorktown)


Name Chandu Visweswariah
Position Research Staff Member and Manager, Circuit and Interconnect Analysis
Department Design Automation, IBM Thomas J. Watson Research Center
Research Interests Circuit simulation, device modeling, circuit optimization, static timing, statistical timing analysis, nonlinear optimization, gradient computation, adjoint methods, VLSI design, timing simulation, design for manufacturability (DFM) and design for profit (DFP), mixed-mode simulation, CAD tools/Design Automation and novel devices.
Contact Information IBM Thomas J. Watson Research Center
1101 Kitchawan Road, Route 134
Yorktown Heights, NY 10598, U.S.A.
Voice: 914-945-3124, IBM tieline 862-3124
Home: 914-271-6118
Cell: 202-253-3972
FAX: 914-945-4469, IBM tieline 862-4469
Email: chandu@us.ibm.com

Contents

Education

Ph.D. Electrical and Computer Engineering Carnegie Mellon University 1989
M.S. Electrical and Computer Engineering Carnegie Mellon University 1986
B.Tech. Electrical Engineering Indian Institute of Technology (Chennai) 1985

Employment

9/1989-present Research Staff Member IBM Thomas J. Watson Research Center
4/2004-present Manager, Circuit and Interconnect Analysis IBM Thomas J. Watson Research Center

Honors and awards

  • IBM Twelfth Plateau Invention Achievement Award, October 2008.
  • IBM Eleventh Plateau Invention Achievement Award, August 2008.
  • IBM Tenth Plateau Invention Achievement Award, May 2008.
  • IBM Ninth Plateau Invention Achievement Award, April 2008.
  • IBM Research Division Outstanding Accomplishment for the EinsStat project, January 2008.
  • Supplemental Patent Issue Award for U.S. Patent 7,117,466 System and method for correlated process pessimism removal for static timing analysis awarded to "the inventors of the top 10% of IBM United States patents that issued during the 2006 calendar year."
  • Supplemental Patent Issue Award for U.S. Patent 7,093,208 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices awarded to "the inventors of the top 10% of IBM United States patents that issued during the 2006 calendar year."
  • IBM Eighth Plateau Invention Achievement Award, December 2007.
  • IBM Outstanding Innovation Award for "EinsStat (Statistical Timing Tool) IP Revenue," July 2007.
  • IBM Seventh Plateau Invention Achievement Award, May 2007.
  • IBM Sixth Plateau Invention Achievement Award, March 2007.
  • IBM Research Division Accomplishment for the EinsStat project, January 2007.
  • The EinsTimer Statistical Timing development team won the EDN (Electronic Design News) Innovator of the Year award, April 2006.
  • EinsTimer Statistical Timing won the EDN (Electronic Design News) Innovation of the Year award in the EDA (Design and Implementation) category, April 2006.
  • IBM Fifth Plateau Invention Achievement Award, January 2006.
  • Selected for the December 2005 EE Times "Great Minds, Great Ideas Project" and special issue. Chandu Visweswariah. He's getting the chips to run on time.
  • Supplemental Patent Issue Award for U.S. Patent 6,826,733 Parameter variation tolerant method for circuit design optimization awarded to "the inventors of the most valuable IBM United States patents that issued during the 2004 calendar year."
  • 2004 Pat Goldberg Memorial IBM Research Best Paper Award in Computer Science, Electrical Engineering and Mathematics for the paper:
    First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan.
    Design Automation Conference (DAC), San Diego, CA, pages 331--336, June 2004.
  • Elected Fellow of the Institute of Electrical and Electronics Engineers (IEEE) for "contributions to large-scale integrated circuits," effective January, 2005.
  • Best paper in the "Back-end design" category, Design Automation Conference (DAC) 2004, San Diego, CA, for the paper:
    First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan.
    Design Automation Conference (DAC), San Diego, CA, pages 331--336, June 2004.
  • 2003 Pat Goldberg Memorial IBM Research Best Paper Award in Computer Science, Electrical Engineering and Mathematics for the paper:
    Statistical timing for parametric yield prediction of digital integrated circuits.
    J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
    Design Automation Conference (DAC), Anaheim, CA, pages 932--937, June 2003.
  • IBM Fourth Plateau Invention Achievement Award, June 2004.
  • IBM Third Plateau Invention Achievement Award, October 2003.
  • IBM Corporate Award for "Formal Static Circuit Tuning Tool," June 2003.
  • IBM Second Plateau Invention Achievement Award, June 2003.
  • The following two papers were selected for the "Best of ICCAD" volume of 40 of the best papers published during 20 years of the International Conference on Computer-Aided Design (ICCAD):
    • C. Visweswariah and R. A. Rohrer, SPECS2: an integrated circuit timing simulator, ICCAD 1987.
    • A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, and C. Visweswariah, Optimization of custom MOS circuits by transistor sizing, ICCAD 1996.
  • Second place, "Best mandatory course 2001/2002," Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands, for teaching "Ontwerptechnologie 5L050" (Design Technology), summer 2002.
  • IBM First Plateau Invention Achievement Award, June 2002.
  • IBM Outstanding Technical Achievement Award for "Invention and development of EinsTuner," December 2001.
  • IBM Execute Now Award for "Design and implementation of the Freeway (G7) microprocessor," July 2001.
  • IBM Research Division Accomplishment for the EinsTuner project, January 2001.
  • IBM Research Division Award for "Expedited release of production EinsTuner," September 2000.
  • Contributions to the INFORMS prize, which was awarded to IBM by the Institute for Operations Research and the Management Sciences, November 1999.
  • IBM Research Division Award for "Design and realization of the Alliance (G5) microprocessor," November 1998.
  • IBM Research Division Award for "Contributions to the design and realization of the Alliance (G4) microprocessor," November 1997.
  • IBM First Patent Application Invention Achievement Award, June 1997.
  • IBM Research Division Accomplishment for the JiffyTune project, January 1997.
  • IBM Blue Chip Award, May 1996.
  • Senior Member, Institute of Electical and Electronics Engineers (IEEE), September 1995.
  • IBM Research Division Technical Group Award for "Contributions to the Alliance first RIT and stand alone bring-up," December 1995.
  • Coauthor, McGraw Hill "Book of the Month," April 1995.
  • IBM Outstanding Technical Achievement Award for "Simulation Program for Electronic Circuits and Systems (SPECS)," May 1994.
  • Fellowship from AT&T Bell Laboratories for the duration of doctoral studies at Carnegie Mellon University.
  • Best Paper in Session, SRC Techcon, October 1988.
  • Best Paper and Presentation, IEEE All-India Students' Symposium on "Recent Trends in CAD," October 1984.

Professional activities

  • Panelist, Net Seminar moderated by Richard Goering, Senior Editor of EE Times, on "The Road to Nanometer CMOS," March 2006. The Net Seminar was part of EE Times' "Great Minds, Great Ideas" project.
  • Organizer, full-day tutorial, "Practical Aspects of Coping with Variability: An Electrical View" at the Design Automation Conference, San Francisco, CA, July 2006. Speakers were Dr. X-W. Lin, Director of R&D, Synopsys, Dr. B. Nikolic, Associate Professor, UC Berkeley, Dr. P. A. Habitz of IBM and Dr. R. Radojcic, Qualcomm.
  • Member, task force on "IBM value-add with silicon modeling and statistical timing," November 2005.
  • Member, PAC2 Technical Program Committee, The Second Watson Conference on Interaction between Architecture, Circuits and Compilers, September 2005.
  • Session chair and panel moderator, special session on "DFM and variability: theory and practice" at the 2005 Design Automation Conference (DAC), Anaheim, CA, June 2005.
  • Focus group discussion leader, "Statistical static timing analysis and optimization: sizzle or fizzle?," at the ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, February 2004.
  • Member, PhD committee of Srinath R. Naidu (advisor: Prof. Ralph H. J. M. Otten), Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands, thesis "Tuning for yield: towards predictable deep sub-micron manufacturing," July, 2004.
  • Panel organizer, "Libraries: lifejacket or straitjacket?" at the Design Automation Conference (DAC), 2003.
  • Member, NSF panel to evaluate "Information Technology Research" proposals, April 2003.
  • Visiting assistant professor on sabbatical assignment, Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands, April to August 2002.
  • Technical Program Committee, Design Automation Conference (DAC), 2003, 2002 and 2001. Sub-committe chair for "Timing and simulation," 2002 and 2003.
  • Organizer, Circuits Education Session seminar series, East Fishkill, NY, 03/2000 to 03/2002.
  • Senior Member, IEEE; member, IEEE Circuits and Systems society.
  • Member, IBM "Futures" team to focus on information technology trends, June 1998.
  • Technical Program Committee, International Conference on Computer-Aided Design (ICCAD), 1998, 1997 and 1996.
  • Technical Program Committee, Custom Integrated Circuits Conference (CICC), 1996.
  • Member, PhD committee of Anirudh Devgan (advisor: Prof. Ronald A. Rohrer), Department of Electrical and Computer Engineering, Carnegie Mellon University, thesis "Adaptively controlled explicit simulation," November, 1993.
  • Member, PhD committee of Kimon Michaels (advisor: Prof. Andrzej Strojwas), Department of Electrical and Computer Engineering, Carnegie Mellon University, thesis "Variable accuracy device modeling for event-driven circuit simulation," March 1993.
  • Technical Program Committee, International Conference on Computer Design (ICCD), 1992.
  • Corporate Ph.D. recruiter at Carnegie Mellon University, 1992 - 1998.
  • Co-chair, IBM internal Circuit Tuning Workshop, 1995.
  • Member, CAD Framework Initiative (CFI) co-simulation and simulation backplane standards committee (1992-1993).
  • Session chair and session organizer of several sessions at the International Conference on Computer-Aided Design (ICCAD), Design Automation Conference (DAC), Custom Integrated Circuits Conference (CICC), International Conference on Computer Design (ICCD), and TAU (ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems) conferences over the years. See curriculum vitae for details.
  • Reviewer for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Circuits and Systems, Design Automation Conference (DAC) and International Symposium on Circuits and Systems (ISCAS).

Significant projects

  • Manager, circuit and interconnect analysis group, since May, 2004. Projects in the group include Maise (interconnect reduced order modeling engine including sensitivity analysis), IBMciao (full-wave mixed circuit and electromagnetic solver), Nova (package and chip power delivery and power integrity analysis) and PDAC (Power Delivery Analysis Convergence).
  • EinsStat (IBM internal only): statistical timing analysis and parametric yield prediction of digital integrated circuits.
  • Deft (IBM internal only) derivative-free tuner for small circuit tuning problems.
  • EinsTuner (IBM internal only): gradient-based circuit optimizer based on static timing analysis.
  • JiffyTune (IBM internal only): gradient-based circuit optimizer based on time-domain circuit simulation.
  • SPECS (IBM internal only): fast transistor-level circuit simulator.
  • Backplane-based mixed mode simulation.

Patents

Granted patents

Granted patents from all countries are listed.
  1. System and method of criticality prediction in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    U.S. patent 7,437,697, issued October 2008.

  2. System and method for statistical timing analysis of digital circuits.
    C. Visweswariah
    U.S. patent 7,428,716, issued September 2008.

  3. Same as above.
    China patent ZL200410078630.7, issued November 2007.

  4. Same as above.
    Japan patent 4,061,295, issued December 2007.

  5. Affinity-based clustering of vectors for partitioning the columns of a matrix.
    K. Kalafala, V. B. Rao, and C. Visweswariah.
    U.S. patent 7,353,359, issued April 2008.

  6. System and method for accommodating non-Gaussian and nonlinear sources of variation in statistical static timing analysis.
    H. Chang, S. Narayan, C. Visweswariah, and V. Zolotov.
    U. S. Patent 7,293,248, issued November 2007.

  7. Method, system and program product for accommodating a spatially correlated source of variation in statistical timing analysis.
    N. Venkateswaran, C. Visweswariah, L. Zhang, and V. Zolotov.
    U.S. patent 7,212,946, issued May 2007.

  8. System and method for correlated process pessimism removal for static timing analysis.
    K. Kalafala, P. Qi, A. J. Suess, D. J. Hathaway, and C. Visweswariah.
    U.S. patent 7,117,466, issued October 2006.

  9. System and method for derivative-free optimization of electrical circuits.
    S. G. Walker, C. Visweswariah, K. Scheinberg, and P. J. Restle.
    U.S. patent 7,117,455, issued October 2006.

  10. System and method for incremental statistical timing analysis of digital circuits.
    C. Visweswariah.
    U.S. patent 7,111,260, issued September 2006.

  11. Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices.
    E. K. Cho, D. J. Hathaway, M-T. Hsu, L. K. Lange, G. A. Northrop, C. Visweswariah, C. Washburn, P. M. Williams, and J. Zhou.
    U.S. patent 7,093,208, issued August 2006.

  12. System and method for probabilistic criticality prediction of digital circuits.
    C. Visweswariah.
    U.S. patent 7,086,023, issued August 2006.

  13. Method of optimizing and analyzing selected portions of a digital integrated circuit.
    D. J. Hathaway, L. K. Lange, C. Visweswariah, and P. M. Williams.
    U.S. patent 7,010,763, issued March 2006.

  14. Method of achieving timing closure in digital integrated circuits by optimizing individual macros.
    D. J. Hathaway, C. Visweswariah, P. M. Williams, and J. Zhou.
    U.S. patent 7,003,747, issued February 2006.

  15. System and method for optimal waveform shaping.
    C. Visweswariah.
    U.S. patent 6,922,819, issued July 2005.

  16. Parameter variation tolerant method for circuit design optimization.
    X. Bai, D. J. Hathaway, P. N. Strenski, and C. Visweswariah.
    U.S. patent 6,826,733, issued November 2004.

  17. Method of reformulating static circuit optimization problems for reduced size, degeneracy and redundancy.
    A. R. Conn and C. Visweswariah.
    U.S. patent 6,321,362, issued November 2001.

  18. Method for incorporating noise considerations in automatic circuit optimization.
    A. R. Conn, R. A. Haring, and C. Visweswariah.
    U.S. patent 5,999,714 issued December 1999.

  19. Method of efficient gradient computation.
    A. R. Conn, R. A. Haring, and C. Visweswariah.
    U.S. patent 5,886,908 issued March 1999.

Patents in the pipeline

Only U.S. filings listed here.
  1. System and method for converting an arbitrary waveform into an effective ramp for timing analysis.
    S. Abbaspour, P. Feldmann, D. D. Ling, and C. Visweswariah.
    Docket YOR-8-2008-????, to be filed.

  2. System and method for variation-aware test pattern generation.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-8-2008-1136, to be filed.

  3. A method for improved Monte Carlo based statistical maximum and minimum operations.
    J. G. Hemmett and C. Visweswariah.
    Docket BUR-9-2008-0376-US1, to be filed.

  4. Methodology to optimize chips for profit weighted performance process and environment variation.
    N. Buck, H. Chen, J. Eckhardt, E. A. Foreman, J. Gregerson, P. A. Habitz, S. Lichtensteiger, and T. Wilder.
    Docket BUR-9-2008-0370-US1, to be filed.

  5. Methods for mixed mode statistical and deterministic timing analysis.
    E. A. Foreman, P. A. Habitz, D. Sinha, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket FIS-9-2008-0368-US1, to be filed.

  6. A method of statistical timing abstraction of VLSI circuits.
    A. Bhanji, B. Dorfman, K. Kalafala, D. Sinha, N. Venkateswaran, and C. Visweswariah.
    Docket FIS-9-2008-0342-US1, to be filed.

  7. System and method for multilayer process space coverage and path selection for at-speed testing.
    Y. Shi, C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2008-0547-US1, to be filed.

  8. Reversible statistical maximum and minimum operations for efficient incremental statistical timing analysis and optimization.
    D. Sinha, N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2008-0317-US1, to be filed.

  9. Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing.
    N. Buck, B. M. Dreibelbis, J. Dubuque, E. A. Foreman, P. A. Habitz, G. M. Schaeffer, and C. Visweswariah.
    Docket BUR-9-2008-0192-US1, filed June 2008.

  10. Methods for statistical slew propagation during block-based statistical static timing analysis.
    J. G. Hemmett, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2008-0093, filed May 2008.

  11. Method for identifying failing timing requirement in a digital design.
    N. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, and C. Visweswariah.
    Docket BUR-9-2008-0057-US1, filed April 2008.

  12. Method and apparatus for statistical path selection for at-speed testing.
    H. Fatemi, C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2007-0613-US1, filed April 2008.

  13. Methods for conserving memory in statistical static timing analysis.
    J. G. Hemmett, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2008-0017-US1, filed March 2008.

  14. Method to identify timing violations outside of manufacturing spec limits.
    N. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, and C. Visweswariah.
    Docket BUR-9-2007-0265-US1, filed March 2008.

  15. Timing closure using multiple timing runs which distribute the frequency of identified fails per timing corner.
    N. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, G. M. Schaeffer, and C. Visweswariah.
    Docket BUR-9-2007-0264-US1, filed February 2008.

  16. Compensating for area of unmatched perimeter density.
    L. S. Chadwick, J. A. Culp, D. J. Hathaway, T. Hook, K. Peterson, A. Polson, C. Visweswariah, and O. Takahashi.
    Docket BUR-9-2007-0267-US1, filed February 2008.

  17. Method and apparatus for computing test margins for at-speed testing.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2007-0614-US1, filed January 2008.

  18. Critical path selection for at-speed test.
    V. Iyengar, D. Lackey, S. Venkatesan, C. Visweswariah, and J. Xiong.
    Docket BUR-9-2007-0146-US1, filed December 2007.

  19. System and method for generating at-speed structural tests to improve process and environmental parameter space coverage.
    G. Grise, P. A. Habitz, V. Iyengar, D. Lackey, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2006-0231-US1, filed November 2007.

  20. Method and apparatus for incrementally computing criticality and yield gradient.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2007-0374-US1, filed October 2007.

  21. Method and device for selectively adding timing margin in an integrated circuit.
    D. Lackey, C. Visweswariah, and P. Zuchowski.
    Docket BUR-9-2007-0075-US1, filed October 2007.

  22. Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits.
    S. Abbaspour, D. J. Hathaway, C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2006-0597-US1, filed April 2007.

  23. IC chip at-functional-speed testing with process coverage evaluation.
    E. A. Foreman, G. Grise, P. A. Habitz, V. Iyengar, D. Lackey, C. Visweswariah, and V. Zolotov.
    Docket BUR-9-2006-0235-US1, filed April 2007.

  24. Parameter ordering for multi-corner static timing analysis.
    N. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    Docket BUR-9-2007-0038-US1, filed February 2007.

  25. Variable threshold system and method for multi-corner static timing analysis.
    N. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    Docket BUR-9-2006-0219-US1, filed February 2007.

  26. Method and system of evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis.
    N. Buck, J. Dubuque, E. A. Foreman, P. A. Habitz, K. Kalafala, P. Qi, C. Visweswariah, and X. Wang.
    Docket BUR-9-2006-0236-US1, filed February 2007.

  27. Method and apparatus for static timing analysis in the presence of a coupling event and process variation.
    S. Abbaspour, G. M. Schaeffer, and C. Visweswariah.
    Docket YOR-9-2006-0628-US1, filed January 2007.

  28. System and method for efficient analysis of point-to-point delay constraints in static timing.
    R. Banerji, D. J. Hathaway, K. Kalafala, J. M. Sheridan, and C. Visweswariah.
    Docket FIS-9-2006-0335-US1, filed December 2006.

  29. Method, system, and program product for computing a yield gradient from statistical timing.
    C. Visweswariah, J. Xiong, and V. Zolotov.
    Docket YOR-9-2005-0500-US1, filed February 2006.

  30. System and method for statistical modeling and statistical timing analysis of integrated circuits.
    J. A. G. Jess and C. Visweswariah.
    Docket YOR-9-2002-0156-US1, filed June 2002.

Publications

Book

  1. Electronic circuit and system simulation methods.
    L. T. Pillage, R. A. Rohrer, and C. Visweswariah.
    McGraw-Hill, 1995.

Book chapter

  1. Electrical and timing simulation.
    C. Visweswariah.
    In Encyclopedia of Electrical and Electronics Engineering, J. G. Webster, Editor, volume 6, pages 229--238, John Wiley and Sons, 1999.

Invited publications

  1. Robustness and quality in the face of variability.
    C. Visweswariah.
    Keynote speech, International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2008.

  2. Within-die variations in timing: from derating to CPPR to statistical methods.
    C. Visweswariah.
    Full-day tutorial, International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 2007.

  3. Statistical techniques to combat variability and achieve robust design.
    C. Visweswariah.
    Invited talk at Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Sapporo, Japan, October 2007.

  4. The end of traditional CMOS.
    C. Visweswariah.
    Panel opening statement at Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Sapporo, Japan, October 2007.

  5. Statistical techniques for robust digital design.
    C. Visweswariah.
    Invited seminar, University of Texas, Austin, TX, March 2007.

  6. Fear, uncertainty and statistics.
    C. Visweswariah.
    Invited talk, International Symposium on Physical Design (ISPD), March 2007, Austin, TX.
    Click here for charts.

  7. What engineers want.
    C. Visweswariah.
    Panel opening statement, Banff International Research Station for Mathematical Innovation and Discovery (BIRS) workshop on "Optimization and Engineering," November 2006, Banff, Alberta, Canada.

  8. Challenges in statistical timing and optimization of integrated circuits.
    C. Visweswariah.
    Invited presentation at Banff International Research Station for Mathematical Innovation and Discovery (BIRS) workshop on "Optimization and Engineering," November 2006, Banff, Alberta, Canada.

  9. Statistical timing in a practical 65 nm robust design flow.
    C. Visweswariah.
    Invited presentation at the C2S2 workshop on Robust Circuit Design, Berkeley, CA, July 2006.

  10. Statistical analysis and optimization in the presence of gate and interconnect delay variations.
    C. Visweswariah.
    Invited presentation at System Level Interconnect Prediction (SLIP), Munich, Germany, page 37, March 2006. Click here for charts.

  11. Can innovation be nurtured?
    C. Visweswariah.
    Invited article for a special issue of EE Times focusing on innovation, December 2005.

  12. Statistical analysis and design of digital integrated circuits.
    C. Visweswariah.
    Invited presentation at EDA Forum '05, Hanover, Germany, November 2005.

  13. Mathematics and engineering: a clash of cultures?
    C. Visweswariah.
    Invited presentation at the Industrial Optimization Seminar Series, The Fields Institute for Research in Mathematical Sciences, Toronto, Canada, May 2005. Click here for streaming audio.

  14. Spread sheet studies on the impact of variability.
    C. Visweswariah.
    Invited presentation at the International Conference on Integrated Circuit Design and Technology (ICICDT '05), Austin, TX, May 2005.

  15. Statistical analysis and design: from picoseconds to probabilities.
    C. Visweswariah.
    Invited tutorial at 17th Symposium on Integrated Circuits and Systems Design (SBCCI), Porto de Galinhas, Brazil, September 2004.

  16. Invited panel statement: New challenges in IC design.
    C. Visweswariah.
    17th Symposium on Integrated Circuits and Systems Design (SBCCI), Porto de Galinhas, Brazil, September 2004.

  17. Invited panel statement: Is statistical timing statistically significant?
    C. Visweswariah.
    Design Automation Conference (DAC), San Diego, CA, June 2004.

  18. Statistical timing of digital integrated circuits.
    C. Visweswariah.
    IEEE International Solid-State Circuits Conference (ISSCC), Advanced Digital Solid-State Circuits Forum, San Francisco, CA, February 2004.

  19. Death, taxes and failing chips.
    C. Visweswariah.
    Design Automation Conference (DAC), Anaheim, CA, pages 343--347, June 2003.

  20. Death, taxes and failing chips.
    C. Visweswariah.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Monterey, CA, December 2002.

  21. Optimization challenges in transistor sizing.
    C. Visweswariah.
    Workshop on Multilevel Optimization in VLSICAD, Institute for Pure and Applied Mathematics (IPAM), University of California at Los Angeles, December 2001.

  22. Overview of continuous optimization advances and applications to circuit tuning.
    A. R. Conn and C. Visweswariah.
    International Symposium on Physical Design (ISPD), April 2001, Sonoma County, CA.

  23. Formal static optimization of high-performance digital circuits.
    C. Visweswariah.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), page 51, December 2000, Austin TX.

  24. Algorithms for formal circuit optimization on a static timing basis. (Part of the full-day tutorial "Static timing analysis and optimization for high-performance digital design success.")
    C. Visweswariah.
    Design Automation Conference (DAC), Los Angeles, CA, June 2000.

  25. Optimization techniques for high-performance digital circuits.
    C. Visweswariah.
    IEEE International Conference on Computer-Aided Design embedded tutorial, San Jose, CA, pages 198--205, November 1997.
    Presentation slides can be viewed by clicking here.

  26. Circuit tuning for high-performance custom digital design.
    C. Visweswariah, S. Sapatnekar, and S. R. Nassif.
    IEEE International Conference on Computer-Aided Design Tutorial, San Jose, CA, November 1996.

  27. Efficient time-domain simulation and optimization of digital FET circuits.
    A. R. Conn, R. A. Haring, and C. Visweswariah.
    Mathematical Theory of Networks and Systems, St. Louis, MO, May 1996.

Refereed publications

  1. Statistical path selection for at-speed test.
    V. Zolotov, J. Xiong, H. Fatemi, and C. Visweswariah.
    International Conference on Computer-Aided Design (ICCAD), November 2008.

  2. Optimal margin computation for at-speed test.
    J. Xiong, V. Zolotov, C. Visweswariah, and P. A. Habitz.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, submitted for review, October 2008.

  3. Statistical path selection for at-speed test.
    V. Zolotov, J. Xiong, H. Fatemi, and C. Visweswariah.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, submitted for review, October 2008.

  4. Statistical modeling and analysis of static leakage and dynamic switching power.
    H. Chen, S. Neely, J. Xiong, V. Zolotov, and C. Visweswariah.
    Power and Timing Modeling, Optimization and Simulation (PATMOS), Lisbon, Portugal, September 2008.

  5. Statistical test to uncover process variations.
    V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah.
    IEEE North Atlantic Test Workshop (NATW), Boxborough, MA, pages 158--164, May 2008.

  6. Optimal margin computation for at-speed test.
    J. Xiong, V. Zolotov, C. Visweswariah, and P. A. Habitz.
    Design Automation and Test in Europe (DATE), Messe Munich, Germany, pages 602--607, March 2008.

  7. Incremental criticality and yield gradients.
    J. Xiong, V. Zolotov and C. Visweswariah.
    Design Automation and Test in Europe (DATE), Messe Munich, Germany, pages 1130--1135, March 2008.

  8. Static timing: back to our roots.
    R. Chen, L. Zhang, V. Zolotov, C. Visweswariah, and J. Xiong.
    Asia and South Pacific Design Automation Conference (ASPDAC), Seoul, Korea, pages 310--315, January 2008.

  9. Compact modeling of variational waveforms.
    V. Zolotov, J. Xiong, S. Abbaspour, D. J. Hathaway, and C. Visweswariah.
    International Conference on Computer-Aided Design (ICCAD), November 2007.

  10. Variation-aware performance verification using at-speed structural test and statistical timing.
    V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah.
    International Conference on Computer-Aided Design (ICCAD), November 2007.

  11. Static timing: back to our roots.
    R. Chen, E. A. Foreman, P. A. Habitz, J. G. Hemmett, K. Kalafala, J. S. Piaget, P. Qi, N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
    ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, pages 130--136, February 2007.

  12. Statistical timing for parametric yield prediction of digital integrated circuits.
    J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, volume 25, number 11, pages 2376--2392, November 2006.

  13. First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, D. K. Beece, J. Piaget, N. Venkateswaran, and J. G. Hemmett.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, volume 25, number 10, pages 2170--2180, October 2006.

  14. Criticality computation in parameterized statistical timing.
    J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    Design Automation Conference (DAC), San Francisco, CA, pages 63--68, July 2006.

  15. Criticality computation in parameterized statistical timing.
    J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), San Jose, CA, pages 119--124, February 2006.

  16. Computation of yield gradients from statistical timing analysis.
    V. Zolotov, J. Xiong, and C. Visweswariah.
    ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), San Jose, CA, pages 125--130, February 2006.

  17. Gate sizing using incremental parameterized statistical timing analysis.
    M. R. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 1029--1036, November 2005.

  18. Parameterized block-based statistical timing analysis with non-Gaussian and nonlinear parameters.
    H. Chang, V. Zolotov, C. Visweswariah, and S. Narayan.
    Design Automation Conference (DAC), Anaheim, CA, pages 71--76, June 2005.

  19. Gate sizing using incremental parameterized statistical timing analysis.
    M. R. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov.
    International Workshop on Logic Synthesis (IWLS), Lake Arrowhead, CA, June 2005.

  20. Parameterized block-based statistical timing analysis with non-Gaussian and nonlinear parameters.
    H. Chang, V. Zolotov, S. Narayan, and C. Visweswariah.
    ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), San Francisco, CA, pages 99--104, February 2005.

  21. Large-scale nonlinear optimization in circuit tuning.
    A. Wächter, C. Visweswariah, and A. R. Conn.
    Future Generation Computer Systems, special issue on the Speedup/PARS workshop in Basel, Germany, Elsevier Science, October 2005, volume 21, number 8, pages 1251--1262.

  22. First-order incremental block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan.
    Design Automation Conference (DAC), San Diego, CA, pages 331--336, June 2004.

  23. First-order parameterized block-based statistical timing analysis.
    C. Visweswariah, K. Ravindran, and K. Kalafala.
    ACM/IEEE international workshop on timing issues in the specification and synthesis of digital systems (TAU), Austin, TX, pages 17--24, February 2004.

  24. Statistical timing for parametric yield prediction of digital integrated circuits.
    J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
    Design Automation Conference (DAC), Anaheim, CA, pages 932--937, June 2003.

  25. Exploiting optimality conditions in accurate static circuit tuning.
    C. Visweswariah, A. R. Conn, and L. G. Silva.
    G. Di Pillo and A. Murli, Editors, High performance algorithms and software for nonlinear optimization, Kluwer Academic Publishers, Dordrect, The Netherlands, pages 363--381, 2003.

  26. Time budgeting in a wireplanning context.
    J. Westra, D-J. Jongeneel, R. H. J. M. Otten, and C. Visweswariah.
    Design and Test in Europe (DATE), Messe Munich, Germany, pages 436--441, March 2003.

  27. Uncertainty-aware circuit tuning.
    X. Bai, C. Visweswariah, P. N. Strenski, and D. J. Hathaway.
    Design Automation Conference (DAC), New Orleans, LA, pages 58--63, June 2002.

  28. Noise considerations in circuit optimization.
    C. Visweswariah, R. A. Haring, and A. R. Conn.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, number 6, volume 19, pages 679--690, June 2000.

  29. Two-step algorithms for nonlinear optimization with structured applications.
    A. R. Conn, L. N. Vicente, and C. Visweswariah.
    SIAM Journal on Optimization, volume 9, number 4, pages 924--947, September 1999.

  30. Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation.
    C. Visweswariah and A. R. Conn.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 244--251, November 1999.

  31. Gradient-based optimization of custom circuits using a static-timing formulation.
    A. R. Conn, I. M. Elfadel, W. W. Molzen, Jr., P. R. O'Brien, P. N. Strenski, C. Visweswariah, and C. B. Whan
    Design Automation Conference (DAC), New Orleans, LA, pages 452--459, June 1999.

  32. Noise considerations in circuit optimization.
    A. R. Conn, R. A. Haring, and C. Visweswariah.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 220--227, November 1998.

  33. JiffyTune: circuit optimization using time-domain sensitivities.
    A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, C. Visweswariah, and C. W. Wu.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, number 12, volume 17, pages 1292--1309, December 1998.

  34. Circuit optimization via adjoint Lagrangians.
    A. R. Conn, R. A. Haring, C. Visweswariah, and C. W. Wu.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 281--288, November 1997.

  35. Inaccuracies in power estimation during logic synthesis.
    D. Brand and C. Visweswariah.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 388--394, November 1996.

  36. Optimization of custom MOS circuits by transistor sizing.
    A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, and C. Visweswariah.
    IEEE International Conference on Computer-Aided Design, San Jose, CA, pages 174--180, November 1996.

  37. Incremental event-driven simulation of digital FET circuits.
    C. Visweswariah and J. A. Wehbeh.
    Design Automation Conference (DAC), Dallax, TX, pages 737--741, June 1993.

  38. Stepsize control in piecewise approximate circuit simulation.
    C. Visweswariah.
    Proc. 5th International Conference on VLSI Design, Bangalore, India, pages 287--292, January 1992.

  39. Piecewise approximate circuit simulation.
    C. Visweswariah and R. A. Rohrer.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. CAD-10(7), pages 861--870, July 1991.

  40. M3 - a multi-level, mixed-mode, mixed A/D simulator.
    R. Chadha, C. Visweswariah, and C-F. Chen.
    IEEE Transactions on Computer-Aided Design of ICs and Systems, 11(5):575--585, May 1992.

  41. Efficient simulation of bipolar digital integrated circuits.
    C. Visweswariah and R. A. Rohrer.
    Design Automation Conference (DAC), San Francisco, CA, pages 32--37, June 1991.

  42. Incorporation of inductors in piecewise approximate circuit simulation.
    C. Visweswariah, P. Feldmann, and R. A. Rohrer.
    IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pages 162--165, November 1990.

  43. Piecewise approximate circuit simulation.
    C. Visweswariah and R. A. Rohrer.
    IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pages 248--251, November 1989.

  44. M3 - a multi-level, mixed-mode, mixed A/D simulator.
    R. Chadha, C. Visweswariah, and C-F. Chen.
    IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pages 258--261, November 1988.

  45. Mixed accuracy simulation with SPECS.
    C. Visweswariah and R. A. Rohrer.
    Proc. SRC Techcon, Dallas, TX, pages 284--286, October 1988.

  46. Model development and verification for high level analog blocks.
    C. Visweswariah, R. Chadha, and C-F. Chen.
    Design Automation Conference (DAC), Anaheim, CA, pages 376--382, June 1988.

  47. SPECS2: an integrated circuit timing simulator.
    C. Visweswariah and R. A. Rohrer.
    IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pages 94--97, November 1987.

  48. Simulation of MOS integrated circuits by the waveform relaxation method.
    C. Visweswariah, T. V. Verghese, and S. Mohan.
    Proc. IEEE All-India Students' Symposium on "Recent Trends in CAD," Tiruchirapalli, India, October 1984.

Other publications, including technical reports

  1. Variation-aware at-speed structural test using statistical timing analysis.
    V. Iyengar, S. Venkatesan, J. Xiong, G. Grise, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah.
    IBM third conference on Chip Testing Best Practices, March 2007.

  2. Compact modeling of variational waveforms.
    V. Zolotov, J. Xiong, S. Abbaspour, D. J. Hathaway, and C. Visweswariah.
    IBM East Fishkill Technical Exchange Conference, October 2007.

  3. Static timing: back to our roots. (IBM internal only)
    C. Visweswariah and V. Zolotov.
    IBM Design Automation Workshop, East Fishkill, NY, March, 2006.

  4. Criticality computation in parameterized statistical timing. (IBM itnernal only)
    J. Xiong, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    IBM Design Automation Workshop, East Fishkill, NY, March, 2006.

  5. Efficient modeling of spatial correlations in parameterized statistical timing. (IBM internal only)
    L. Zhang, V. Zolotov, C. Visweswariah, and N. Venkateswaran.
    IBM Design Automation Workshop, East Fishkill, NY, March, 2006.

  6. Computation of yield gradients from statistical timing analysis. (IBM internal only)
    V. Zolotov, J. Xiong, and C. Visweswariah.
    IBM Design Automation Workshop, East Fishkill, NY, March, 2006.

  7. Statistical-based analysis and design for VLSI ASICs and systems-on-chip (SoCs).
    G. W. Doerre and C. Visweswariah.
    EDTS white paper (2nd version), June, 2005.

  8. Statistical timing analysis in support of robust integrated circuit design and optimization.
    D. K. Beece, J. G. Hemmett, K. Kalafala, J. Narasimhan, S. Narayan, J. S. Piaget, N. Venkateswaran, C. Visweswariah, and S. G. Walker.
    IBM Academy Conference on Design for Manufacturability, Somers, NY, May, 2004.

  9. Hierarchical statistical modeling of integrated circuit variability.
    Y. Amemiya and C. Visweswariah.
    IBM Academy Conference on Design for Manufacturability, Somers, NY, May, 2004.

  10. Variability-aware design optimizations using statistical timing.
    M. Guthaus, D. Kung, J. Narasimhan, R. Puri, L. Trevillyan, and C. Visweswariah.
    IBM Academy Conference on Design for Manufacturability, Somers, NY, May, 2004.

  11. Statistical timing and yield prediction of digital integrated circuits.
    S. R. Naidu, C. Visweswariah, J. A. G. Jess, and R. H. J. M. Otten.
    Eindhoven University of Technology, Eindhoven, The Netherlands, Technical report, Department of Electrical Engineering, August 2002.

  12. Ontwerptechnologie 5L050 class notes and teaching materials.
    C. Visweswariah.
    Eindhoven University of Technology, Eindhoven, The Netherlands, Technical report, Department of Electrical Engineering, June 2002.
    Only static timing and sensitivity class notes available in softcopy form.

  13. Computation and chain-ruling of MOSFET sensitivities.
    C. Visweswariah.
    IBM Research Division, T. J. Watson Research Center, Technical Report, February 2002.

  14. White paper on the future of formal static tuning (IBM internal only).
    C. Visweswariah.
    IBM Internal White Paper, January 2000.

  15. Noise considerations in circuit optimization.
    C. Visweswariah, R. A. Haring, and A. R. Conn.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 21505(97014), June 1999.

  16. Two-step algorithms for nonlinear optimization with structured applications.
    A. R. Conn, L. N. Vicente, and C. Visweswariah.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 21198(94689), June 1998.

  17. Electrical and timing simulation.
    C. Visweswariah.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 21191(94676), May 1998.

  18. JiffyTune: circuit optimization using time-domain sensitivities.
    A. R. Conn, P. K. Coulman, R. A. Haring, G. L. Morrill, C. Visweswariah, and C. W. Wu.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 20963(92837), August 1997.

  19. Inaccuracies in gate-level power estimation.
    D. Brand and C. Visweswariah.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 20520, August 1996.

  20. Circuit simulation notes.
    C. Visweswariah.
    Class notes, IBM T. J. Watson Research Center, Yorktown Heights, NY, December 1992.

  21. SPECS users' guide versions 4.06 to 4.23.
    A. McDonald and C. Visweswariah.
    Technical report, IBM Microelectronics, Burlington VT, October 1994.

  22. Variable accuracy circuit simulation with SPECS.
    C. Visweswariah.
    Proc. IBM ITL on Design Automation, Kingston, NY, October 1990.

  23. Incorporation of inductors in piecewise approximate circuit simulation.
    C. Visweswariah, P. Feldmann, and R. A. Rohrer.
    IBM Research Division, T. J. Watson Research Center, Research Report RC 15773, November 1990.

  24. Workshop notes.
    C. Visweswariah, P. Feldmann, A. D. Stein, and X. Zhang.
    SRC-CMU Technology Transfer Course, Carnegie Mellon University, Pittsburgh, PA, August 1989.

  25. Experiments with SPECS at Harris Semiconductor.
    M. Chian and C. Visweswariah.
    Technical report, Harris Semiconductor, Melbourne, FL, March 1989.

  26. Piecewise approximate circuit simulation.
    C. Visweswariah.
    Technical Report CMUCAD-89-28, Carnegie Mellon University, Pittsburgh, PA, May 1989.

  27. Circuit simulation with SPECS.
    C. Visweswariah.
    Technical report, Harris Semiconductor, Melbourne, FL, August 1988.

  28. Data structures for the new MOTIS.
    C. Visweswariah, T. Sheng-Lin, E. Szeto-Lee, R. Chadha, and C-F. Chen.
    Technical report, AT&T Bell Laboratories, Murray Hill, NJ, December 1987.

  29. Conversion of Laplace and Z transforms into state-space representations and its automation.
    K. Singhal, R. Chadha, and C. Visweswariah.
    Technical report, AT&T Bell Laboratories, Murray Hill, NJ, May 1987.

  30. ACME - an analog C model verification tool.
    C. Visweswariah.
    Technical report, AT&T Bell Laboratories, Murray Hill, NJ, January 1987.

  31. SPECS2: a timing simulator.
    C. Visweswariah.
    Technical Report CMUCAD-86-24, Carnegie Mellon University, Pittsburgh, PA, October 1986.

  32. WARMOSS: a time-domain integrated circuit simulator based on waveform relaxation.
    C. Visweswariah.
    Technical report, Indian Institute of Technology, Chennai, India, May 1985.
    Bachelor's thesis.

Publicity

Articles in the press and on the web.
  1. Statistical timing tool moves from interesting to necessary.
    R. Wilson.
    EDN magazine, June 6, 2008.

  2. Who needs statistical timing and how to use it.
    R. Goering.
    SCD Source "Expert's Corner," November 1, 2007.

  3. Patent claims imperil statistical standards push.
    R. Goering.
    EE Times, June 15, 2007.

  4. Rethinking statistical timing analysis.
    R. Goering.
    EE Times, April 2, 2007.

  5. Chandu Visweswariah: IBM innovation brings statistics to digital-IC design.
    M. Santarini.
    EDN Magazine, May 11, 2006.

  6. Selected for the 12/2005 EE Times "Great Minds, Great Ideas Project" and special issue. Chandu Visweswariah. He's getting the chips to run on time.
    EE Times, Inventor profile, December 5, 2005. Also an essay on innovation.

  7. He's getting the chips to run on time.
    EE Times, November 28, 2005.

  8. Variability upends designers' plans.
    R. Goering.
    EE Times, November 21, 2005.

  9. IBM claims edge on EDA guard in statistical tools.
    R. Goering.
    EE Times, June 6, 2005.

  10. IBM makes EDA play -- offers commercial statistical timing tool.
    M. Santarini.
    EDN Magazine, June 2, 2005.
    Also available at World business news wire.

  11. IBM markets statistical timing analyzer.
    R. Goering.
    EE Times, June 3, 2005.
    Also available at EEProductCenter.com.

  12. IBM opens doors on statistical timing analysis suite.
    Online staff.
    Electronic News, June 3, 2005.

  13. IBM to offer 'statistical timing' solutions for chip designers: Press releases
  14. Statistical analysis moves past 'normal.'
    R. Goering.
    EE Times, March 7, 2005.

  15. Statistical tool shift: it's all in the timing.
    R. Goering.
    EE Times, February 14, 2005.

  16. Designers wary as IBM embraces statistical timing.
    D. Lammers.
    EE Times, February 9, 2004.

  17. IBM uses "EinsStat" statistical analysis timing tool.
    D. Lammers.
    EE Times, February 3, 2004.

  18. Age of 'variability' dawns.
    M. Santarini and N. Mokhoff.
    EE Times, June 9, 2003.

  19. Statistical analysis to yield better chips.
    M. Santarini.
    EE Times, March 28, 2003.

  20. Tau's timing gurus rally for statistical analysis; Researchers: Time to overhaul design.
    R. Goering and R. Wilson.
    EE Times, Issue 1248, December 9, 2002, pages 1, 100, article referencing "Death, Taxes and Failing Chips," invited presentation at TAU 2002.

  21. IBM tool automates resizing of transistors.
    D. Lammers.
    EE Times, Issue 1222, June 10, 2002, pages 51, 60, article on EinsTuner.

  22. IBM gets refined with chip software.
    S. Shankland.
    CNET news.com, May 31, 2002, article about EinsTuner. The same article in Chinese appeared in the Chinese version of CNET, http://www.ccw.com.cn.

  23. Chip Checker: EinsTuner automates the transistor-design process.
    S. Wolpin.
    IBM Think Research, http://www.research.ibm.com/thinkresearch, July 2002.

  24. Automatic circuit tuning.
    IBM Research Magazine, number 1, April 1997, page 8, article about JiffyTune.

Chandu Visweswariah chandu@us.ibm.com


Last updated 13 Nov 2008

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