Publications

Journal Publications

1. TETA: Transistor-Level Waveform Evaluation for Timing Analysis
   E. Acar, F. Dartu and L. T. Pileggi, IEEE Trans. On Computer Aided Design,May 2002.

1. Full-chip Leakage Estimation Considering On-chip Environmental and Process Variations
   A. Devgan, E. Acar, H. Su, Y. Liu and S. Nassif,submitted to International Conference on Computer Aided Design, 2003, Nov 2003.
2. Leakage and Leakage Sensitivity Computation for Combinational Circuits
   E. Acar, A. Devgan, R. Rao, Y. Liu, S. Nassif and H. Su,Proceedings of International Symposium on Low Power Electronics and Design 2003, Aug 2003.
3. Full Chip Leakage Estimation Considering Power Supply and Temperature Variations
   H. Su, Y. Liu, A. Devgan, E. Acar and S. Nassif, Proceedings of International Symposium on Low Power Electronics and Design 2003, Aug 2003.
4. Power Grid Reduction Based on Algebraic Multigrid Principles
   H. Su, E. Acar and S. Nassif, Proceedings of Design Automation Conference 2003, Jun 2003.
5. Optimal Shielding/Spacing Metrics For Low Power Design
   R. Arunachalam, E. Acar and S. Nassif, Proceedings of IEEE Annual Symposium on VLSI, Feb 2003.
6. Predicting Short Circuit Power From Timing Models
   E. Acar, R. Arunachalam and S. Nassif, Proceedings of Asia Pacific Design Automation Conference 2003, (ASPDAC), Jan 2003.
7. A Linear Centric Simulation Framework for Parameter Fluctuations
   E. Acar, L. T. Pileggi, S. Nassif, Proceedings of Design Automation Conference of Europe 2002 (DATE), Mar 2002.
8. Time-Domain Simulation of Variational Interconnect Models
   E. Acar, S. Nassif, Y. Liu and L. Pileggi, Proceedings of International Symposiumon Quality Electronic Design 2002 (ISQED), Mar 2002.
9. Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations
   E. Acar, S. Nassif, Y. Liu and L. Pileggi, Proceedings of International Symposiumon Quality Electronic Design 2001 (ISQED), Mar 2001.
10. Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.
    E. Acar, S. Nassif, Y. Liu and L. Pileggi,ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems (TAU), Dec 2000.
11. S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric
    E. Acar, A. Odabasioglu, M. Celik and L. T. Pileggi, Proceedings of Great Lakes Symposium on VLSI (GLS-VLSI) 1999, Mar 1999.
12. H-gamma: A Delay Metric Based on Gamma Density Approximation of Homogenous Response
    T. Lin, E. Acar and L. Pileggi,Proceedings of International Conference on Computer Aided Design 1998 (ICCAD), Nov 1998.
13. Looking Beyond the Elmore Delay - Metrics for Deep Submicron
    T. Lin, E. Acar and L. Pileggi, Proceedings of Semiconductor Research Corporation Technical Conference 1998 (TECHCON), 1998.
14. Regressor Based Adaptive Infinite Impulse Response Filtering
    E. Acar and O. Arikan, Proceedings of International Conference on Acoustics, Speech and Signal Processing 1998 (ICASSP), June 1998.
15. Effective Algorithms for Regressor Based Adaptive Infinite Impulse Response Filtering
    E. Acar and O. Arikan, Proceedings of International Symposium on Circuits and Systems 1998, (ISCAS), May 1998.

1. Method and system for power node current waveform modeling, with Sani Nassif, filed on Sep 2002.
   
2. A Method for predicting short-circuit current and energy, with Sani Nassif and Ravishankar Arunachalam, filed on Jan 2003.
   
3. Method for efficiently computing average leakage in combinational circuits, with Anirudh Devgan, Frank Liu, Rahul Rao and Sani Nassif. Filed on Jun 2003.
   

1. Full Chip Leakage Estimation Considering Power Supply and Temperature Variations, w/ Haihua Su, Ying Liu, Anirudh Devgan, Sani Nassif
   
2. Power Grid Reduction Based on Algebraic Multigrid Principles, w/ Haihua Su, Sani Nassif
   
3. Evaluation Method and Metrics of Shielding/Spacing Approaches for Coupling Avoidance, w/ Ravishankar Arunachalam and Sani Nassif, RC22584
   
4. Advanced Waveform Models for the Nano-Meter Regime, Sani Nassif, Emrah Acar, RC22709
   
5. Linear Centric Simulation Approach for Timing Analysis. E. Acar, Ph.D. Dissertation, Dec 2001.
   
6. Assessment of Worst Case Circuit Performance Under Interconnect Variations. E. Acar, SRC Tech. Report.Task 779.002. Task leaders: Andrzej J. Strojwas and L. T. Pileggi, 2000.
   
7. S2P: A new accurate metric for RC interconnects. A. Odabasioglu, E. Acar, M. Celik and L. T. Pileggi. Tech. Report, Center for Electronic Design Automation, Carnegie Mellon University, 1999.
   
8. h-gamma: An RC Delay Metric Based on a Gamma Distribution Approximation of the Homogeneous Response; T. Lin, E. Acar and L. Pileggi,SRC Tech. Report. Task 069.068. Task Leader: L. T. Pileggi, 1998.
   
9. Regressor Based Adaptive Infinite Impulse Response Filtering. E. Acar, M.S. Thesis, July 1997.
   
10. TETA: Transistor-Level Waveform Evaluation for Timing Analysis. E. Acar, F. Dartu and L. T. Pileggi, IBM Technical Report

1. Poster presentations at Gigascale Silicon Research Center, Annual Review meetings, 1999, 2000 and 2001.
   
2. Poster presentation at GSRC/Marco Interconnect Center Annual Review 2000.
   
3. Presentations at Industrial Affiliates Day, Dept. of Electrical and Computer Engineering, Carnegie Mellon University. 1998 and 1999.