"A Method to Compute Critical Area with Shapes Biasing", R. J. Allen, P. Chan, E. Papadopoulou, S. Braasch, M. Y. Tan, Docket BUR920040216, filed with the U.S. Patent Office, February 2005
"Optimized placement of sub-resolution assist features within two-dimensional environments", R. Gordon, A. Lvov, S. Mansfield, M. Mukherjee and E. Papadopoulou, Docket FIS920030380US1, filed with the U.S. Patent Office, April 2004
“IC design modeling allowing Dimension-dependent rule checking”, E. Papadopoulou and D. Maynard, Docket BUR920030149US1, filed with the U.S. Patent Office, February 2004
“Critical Area Computation of composite fault mechanisms using Voronoi diagrams”, R. Allen, E. Papadopoulou, M.Y. Tan, Docket BUR920030136US1, filed with the U.S. Patent Office, March 2004
“Method and system for determining Critical Area for missing material defects in circuit layouts'', E. Papadopoulou, US6317859, issued November 2001
“Method and system for determining Critical Area for circuit layouts”, E. Papadopoulou and D.T. Lee, US6178539, issued January 2001
“An incremental method for Critical Area and Critical Region computation of via blocks”, E. Papadopoulou, M. Lavin, G. Tellez, and A. Allen, US6247853, issued June 2001
“Incremental Critical Area Computation for VLSI Yield Prediction'', E. Papadopoulou and M. Lavin, US 6044208, issued April 2000.