Publications

向华 Publications listed on DBLP

Journal Papers

  1. Hua Xiang, Kai-Yuan Chao, and Martin D. F. Wong. An ECO Routing Algorithm for Eliminating Coupling Capacitance Violations, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006. (PDF)
  2. Hua Xiang, Xiaoping Tang, and Martin D. F. Wong. An Algorithm for Integrated Pin Assignment and Buffer Planning, ACM Transactions on Design Automation of Electronic Systems, 2005. (PDF)
  3. Hua Xiang, Xiaoping Tang, and Martin D. F. Wong. Bus-Driven Floorplanning, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 11, pp 1522-1530, November, 2004. (PDF)
  4. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, and I-Min Liu. A Polynomial Time-Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 1, pp 141-147, January, 2004. (PDF)
  5. Hua Xiang, Xiaoping Tang, and Martin D. F. Wong. Min-cost Flow Based Algorithm for Simultaneous Pin Assignment and Routing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 7, pp 870-878, July, 2003. (PDF)
  6. Wenkui Ding, Jianping Wang, Hua Xiang, Chuoqun Hsu and Xiaoming Li. The Implementation and Optimal Strategies of Out_of_Core Computing in p_HPF Parallel Compiling System, Chinese Journal of Computers, Vol. 22, No. 10, pp 1042-1049, October, 1999.

Conference Papers
  1. Hua Xiang, Liang Deng, Li-Da Huang and Martin D.F. Wong, OPC-Friendly Bus Driven Floorplanning, International Symposium on Quality Electronic Design, San Jose, CA, March, 2007. (PDF)
  2. Hua Xiang, Kai-Yuan Chao, Ruchri Puri and Martin D.F. Wong, Is Your Layout Density Verification Exact - A Fast Exact Algorithm For Density Calculation, Proceedings of International Symposium on Physical Design, Mar. 2007. (PDF)
  3. Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao and Martin D.F. Wong, Dummy Fill Density Analysis with Coupling Constraints, Proceedings of International Symposium on Physical Design, Mar. 2007. (PDF)
  4. Liang Deng, Martin D. F. Wong, Kai-Yuan Chao and Hua Xiang, Coupling aware dummy metal insertion for lithography, Proceedings of SPIE, Vol. #652, Feb. 2007.
  5. Liang Deng, Martin D.F. Wong, Kai-Yuan Chao, and Hua Xiang, Coupling-aware dummy metal insertion for lithography, Proc. Asia and South Pacific Design Automation Conf., Jan. 2007. (PDF)
  6. Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, Wire Density Driven Global Routing for CMP Variation and Timing, Proc. International Conference on Computer Aided Design, Nov, 2006. (PDF)
  7. Hua Xiang, Li-Da Huang, Kai-Yuan Chao, and Martin D. F. Wong. An ECO Algorithm for Resolving OPC and Coupling Capacitance Violations. International Conference on ASIC, Shanghai, China, 2005. (PDF)
  8. Hua Xiang, I-Min Liu, and Martin D. F. Wong. Wire Planning with Bounded Over-the-Block Wires. International Symposium on Quality Electronic Design, pp 622-627, San Jose, CA, March, 2005. (PDF)
  9. Hua Xiang, Kai-Yuan Chao, and Martin D. F. Wong. Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. International Symposium on Quality Electronic Design, pp 181-186, San Jose, CA, March, 2005. (PDF)
  10. Hua Xiang, Kai-Yuan Chao, and Martin D. F. Wong. An ECO Algorithm for Eliminating Crosstalk Violations, ACM/SIGDA 2004 International Symposium on Physical Design, pp 41-46, Phoenix, Arizona, April, 2004. (PDF)
  11. Hua Xiang, Xiaoping Tang, and Martin D. F. Wong. Bus-Driven Floorplanning, IEEE/ACM International Conference on Computer Aided Design, pp 66-73, San Jose, CA, November, 2003. (PDF)
  12. Seokjin Lee, Hua Xiang, Martin D. F. Wong, and Richard Y. Sun. Wire Type Assignment for FPGA Routing, ACM International Symposium on Field-Programmable Gate Arrays, pp 61-67, Monterey, CA, February, 2003. (PDF)
  13. Hua Xiang, Kai-Yuan Chao, and Martin D. F. Wong. ECO Algorithms for Removing Overlaps between Power Rails and Signal Wires, IEEE/ACM International Conference on Computer Aided Design, pp 67-74, San Jose, CA, November, 2002. (PDF)
  14. Hua Xiang, Xiaoping Tang, and Martin D. F. Wong. An Algorithm for Integrated Pin Assignment and Buffer Planning, ACM/IEEE Design Automation Conference, pp 584-589, New Orleans, LA, June, 2002. (PDF)
  15. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, and I-Min Liu. A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem, Design, Automation and Test in Europe, pp 470-475, Paris, France, March 2002. (PDF)
  16. Hua Xiang, Xiaoping Tang, and Martin D. F. Wong. An Algorithm for Simultaneous Pin Assignment and Routing, IEEE/ACM International Conference on Computer Aided Design, pp 232-238, San Jose, CA, November, 2001. (PDF)
  17. Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong, and Hua Xiang. A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints, IEEE/ACM International Conference on Computer Aided Design, pp 49-56, San Jose, CA, November, 2001. (PDF)
  18. Hua Xiang, Xiaoping Tang, and Martin D. F. Wong. Simultaneous Pin Assignment and Routing, The Tenth Workshop on Synthesis And System Integration of Mixed Technologies, Nara, Japan, October, 2001.
  19. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, and I-Min Liu. An Exact Diode Insertion/Routing Algorithm for Fixing Antenna Problem, The Tenth Workshop on Synthesis And System Integration of Mixed Technologies, Nara, Japan, October, 2001.
  20. Jianping Wang, Hua Xiang, Chuoqun Hsu, and Xiaoming Li. The Implementation and Optimizations of an Out_of_Core Model in p_HPF Compiler, Advanced Parallel Processing Technologies '99, Changsha, China, October, 1999.
  21. Hua Xiang, Gengbin Zheng, Lixia Shi, Jianping Wang and Chuoqun Hsu. Methods Used in p_HPF Compiler System to Process Some Typical Problems and Analyses of the Test on DAWNING Platform, DAWNING 1000 Conference, pp 214-223, Beijing, China, October, 1998.


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