Interpretation of Rent's Rule for Ultralarge-scale Integrated Circuitry
Computer hardware components have changed significantly since the 1960s, 1970s, 1980s, and even since the early 1990s. Work concerning Rent's memos prior to this project has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent while working at IBM, even though today's computer components are significantly different from those in 1960 and 1971. However, because of the significant changes in the design and implementation of computer hardware components since 1960 and 1971, a new interpretation of Rent's memos is needed for today's components. We have obtained copies of Rent's two memos. In these memos, Rent describes the method that he used to obtain an empirical relationship between properties of the computer hardware components of the IBM 1401 and IBM 1410 computers. We have studied the memos carefully in order to understand Rent's original intent. Based on our careful reading of these two memos, the personal knowledge of one of us with the 1401 and 1410 computers, and our experience designing ultralarge-scale integrated (ULSI) circuits for high-performance microprocessors, we have derived an historically equivalent interpretation of Rent's memos suitable for today's computer components. The purpose of this project is to present a new interpretation of the memos and to present an application to wirelength distributions of real ULSI circuitry. In this project we describe the contents of the memos, provide an historically-equivalent interpretation of the memos for today's computer components, and apply this new interpretation to real ULSI control logic circuitry in the 1.3-GHz IBM POWER4 microprocessor. The results obtained during this work show that the new interpretation of the two memos provides improved wirelength distribution models with better qualitative agreement with measurements and more accurate estimates of wirelength distributions and wirelength requirements for real ULSI designs compared with prior methods.
This figure shows a visual depiction of computer hardware described by Rent in his two 1960 memos (a), a card schematic (b), and a method to calculate Rent's parameters. In (a), the shaded small squares in cards A, B, and C represent used circuits, the white squares represent unused circuits, the solid lines pointing downward below cards A, B, and C represent used edge connectors, the dashed squares in D, E, and F represent unused cards, the dotten solid lines pointing downward below cards D, E, and F represent unused edge connectors, and the dashed curved lines between the two chassis represent that these connections are not included by Rent in his calculation.
The figure below shows a visual depiction of the historically-equivalent interpretation of Rent's memos for ULSI circuit designs. In particular, (a) represents a schematic of several current designs, including clocking circuitry, (b) shows examples of a gate and a connection, (c) shows a method to calculate Rent's parameters. In (a), the dark shaded gates represent used gates, which are gates used in the functional logic of the design; the white gates represent unused gates, and the light gray gates represent gates that are associated with clocking circuitry, such as LCBs (local clock buffers) and LCBDRVs (local clock buffer drivers). The dashed white squares represent IO pins, the dotted lines represent unused nets, the solid lines represent used nets, and the dashed lines represent nets that are associated with clocking circuitry.
On-chip Interconnect Requirements
This project addresses the need for ultralarge-scale integrated (ULSI) chip design data for an assessment of existing on-chip wirelength distribution models. In this project, data extracted from modern chips such as high-performance microprocessors provide information about actual wirelength requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by evaluating existing models as functions of Rent's parameters that are extracted from the designs. This brief assesses the extent to which existing models are able to estimate wirelength requirements in 100 ASIC-like control logic designs in the 1.3-GHz POWER4 microprocessor. For each design, physical design characteristics and wirelength requirements are measured and compared with model estimates. Possible reasons that may explain the lack of agreement are also investigated in this project.
Statistical models for the VLSI route problem: Estimating the efficiency of collaborative problem-solving, with applications to chip design In complex processes such as ultra large scale integration (ULSI) of chips, computer-aided design tools are treated as black boxes in the typical chip design process. In most cases, the automated design tools operate on designs and successfully complete a specified task to create designs that satisfy specified design criteria. In other cases involving complex designs, however, the tools are unable to create designs that satisfy the specified criteria. In both situations, the performance of the tools can be enhanced with systematic external intervention that is implemented with some supplemental algorithm. This algorithm can either be fully automated or can rely on formally describable human expertise. In this intervention, the supplmental algorithm and the automated design tool take turns to move the design from one configuration to anohter until either the task is complete or until further improvements are not possible or necessary. In such as setting, a number of questions arise about how to measure the effectiveness of the external intervenion. One question, for example, is whether the external intervention is consistently able to assist the automated program to make progress. This situation is an instance of a general problem involving collaboration of several contributors who strive to achieve a certain goal, and we have developed a statistical framework to address questions that arise in the context of such problems. As an example, we apply this framework to the problem of routing a functional unit of the IBM POWER4 microprocessor.
Physics tells us that there are limits for shrinking wires and devices. So better design techniques are more important as these physical limits are reached, and better design can help achieve more with available technology. Currently, assistance is provided by individual designers in an ad hoc way described as "carefully managed engineered wires and custom routes" that are costly to implement.
In chip design, success is a chip that operates at the project frequency and meets a set of other constraints specified by current engineering requirements. Examples of such constraints are the chip real estate (that is, chip area) and power dissipation limits. Within this set of traditional constraints, many possible designs exist that simultaneously enhance the design with respect to other parameters such as critical area, total wire length, via count, or parasitic coupling.
For a particular chip architecture, success is achieved by feeding a device layout to an automated route algorithm, which fails on complex designs. In this project, we developed a set of equations to identify poor routes for routing by a supplemental algorithm, with the route algorithm completing the remaining routes. Each iteration of this loop is a trial, and the sequence of trials is continued until either success is achieved or one decides to obtain a better design. Our statistical models will help with such decisions, as illustrated in the diamond box in the figure below. To start, we locate the most poorly-routed signals within the chip area. The region occupied by these wires defines a "region of influence" of the supplementary algorithm and divides the wires into three sets, namely:
For each group, we define effectiveness variables for wirelengths and vias. Our assumptions about these variables are based on how we believe the supplemental algorithm will interact with the automated router, and we find no evidence in the data to contradict our assumptions. First, we postulate that the effectiveness variables are random variables following a multivariate normal distribution; that the variables observed in different trials are mutually independent; that the means and correlation structure within a trial are invariant from trial to trial; and that the variances are inversely proportional to domain size. Here, we use the term "domain size" to describe the amount of wire or via count in each of the three sets of routes.
Next, we evaluate the effectiveness of the supplemental algorithm, and whether progress is being made. We evaluate a weighted average of each effectiveness based on a series of trials, evaluate the standard errors and correlation structure, and establish the significance of the observed effects by calculating p-values and confidence bounds. If we succeed to obtain a legal route solution after a series of trials, we can stop or we can try to improve the design further. To assist in making this decision, we forecast the effectiveness of the supplemental algorithm in a subsequent step and establish its significance.
We applied these statistical frameworks to the wire routes in the POWER4 Instruction Fetch Unit. The immediate problem is that an automated vendor router tries but fails to wire this section. A supplemental algorithm (human intervention) commits to six trials to help the router succeed, and in the process reduced via count by 20 percent with no negative impact on wirelength, where the division of labor between human intervention and the vendor router is 1/3:2/3. The human intervention had significant positive effect on both wirelength and via count, with only slight negative impact on the router in the regions of influence, and with no impact on the vendor router outside the region of influence. To decide whether it is worthwhile to continue additional trials, we use our statistical model of forecasting and find strong evidence for negative impact on wirelength with no impact on via count; this reduces the cumulative wirelength effectiveness at trial 7. We see that it is not profitable to continue, so we stop.
The ability to make these types of decisions provides a method for designers to make efficient use of their design efforts. For example, if there are two weeks remaining in a design schedule, the ability to make the decision to stop then frees the designers to focus their efforts elsewhere.
Characterization of the Capacitive Load on a Global Clock Distribution
Power reduction techniques are a critical issue in the design of todaay's ultra-large-scale integrated (ULSI) chips. This project is concerned with methods to characterize the capacitive load on the POWER4 on-chip global clock distribution, which is a large contributor to the overall chip power dissipation. A characterization of the capacitive load is needed because the contributions of the on-chip devices and interconnections are typically overestimated and are not well understood for high performance microprocessors. One problem that results from the lack of this information is excessively high power dissipation in the chip global clock distribution; the global clock distribution is over-designed and stronger than necessary to drive the actual (lower) chip load. Information about the capacitive load is difficult to obtain because the data volume is large, and extracting the interconnect data is a complex task. Sophisticated computer software is needed to extract the circuit and physical design data for hundreds of devices and wire segments within the chip design schedule.
This project presents the first comprehensive characterization of the clock load for ASIC-like (application-specific integrated circuit) control logic designs in the 1.3GHz POWER4 microprocessor core. This characterization was achieved with the use of sophistical software written for this study to accomplish the task of extracting the data from these designs. Analysis of the data shows that the wire contribution to the chip capacitive load is significant and can increase the capacitive load of a design by 30% on average and by as much as 130% for some designs. The results also suggest that the wire load contribution on each metal layer can be reduced if an alternate interconnect style is selected. Two alternate design styles are presented and show that a capacitive load reduction of 8.4% to 20% is expected for each design. Extended to the entire chip, the results show that the load reduction for the core is expected to be as high as 10%. These values are large enough that one alternate design style has been implemented in the design methodology of future chips, including the POWER5 microprocessor.
Wafer Yield Modelling
Contributed: "Defects Modeling and Yield Forecasting in Semiconductor Manufacturing"
Invited: "Wafer Yield Modelling"
Invited: "Wafer Yield Modelling"
Contributed: "Statistical Aspects of VLSI Yield Modelling"
Invited: "The Mechanical Design of Low K/Copper Interconnect Structures"