IBM Research Reports

These Non-Confidential IBM Research Reports are available for download at IBM Research Cyber Digest

Yield

  • "Factorial analysis and forecasting of integrated-circuit yield," M. Baron, A. Takken, E. Yashchin, M. Lanzerotti, IBM Research Report RC23386, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, October 21, 2004.

    • Rent's rule for ultralarge-scale integrated circuitry, and applications

  • "Accounting for Circuitry Type in Assessments of Wire-Length Distribution Models for ULSI Chips," G. Fiorenza, R. Rand, M. Y. Lanzerotti, IBM Research Report RC23506, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, January 27, 2005.

  • "Methods for Accurate Wirelength Estimation of Functional Circuitry in ULSI Chips," M. Y. Lanzerotti, G. Fiorenza, R. Rand, IBM Research Report RC23505, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, January 27, 2005.

  • "Predicting Interconnect Requirements in Ultra-Large-Scale Integrated Control Logic Circuitry," M. Y. Lanzerotti, G. Fiorenza, R. A. Rand, IBM Research Report RC23500, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, January 21, 2005.

  • "Interpretation of Rent's Rule for ultralarge-scale integrated circuit designs, with application to wire-length distribution models," M. Y. Lanzerotti, G. Fiorenza, R. Rand, IBM Research Report RC22854, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, July 23, 2003.

  • "Wire-length distributions for signals associated with functional logic circuitry and synchronization circuitry in ultralarge-scale integrated circuit designs," M. Y. Lanzerotti, G. Fiorenza, R. Rand, IBM Research Report RC22869, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, August 13, 2003.

    • On-chip interconnect requirements

  • "Characterization of the Impact of Interconnect Design on the Capacitive Load Driven by a Global Clock Distribution," G. G. Lopez (Georgia Tech), G. Fiorenza, T. J. Bucelot, P. J. Restle, M. Y. Lanzerotti, IBM Research Report, RC23501, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, January 21, 2005.

  • "The assessment of on-chip wire-length distribution models," M. Y. Lanzerotti Wisniewski, G. Fiorenza, R. Rand, IBM Research Report RC22853, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, July 22, 2003.

    • Statistical models for the VLSI route problem

  • "The physical design of on-chip interconnections, Part I: Quantification of Interconnect Properties," M. Y. Lanzerotti Wisniewski, E. Yashchin, R. L. Franch, D. P. Conrady, D. Maynard, G. Fiorenza, I. C. Noyan, IBM Research Report RC-22345, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, January 20, 2002.

  • "The physical design of on-chip interconnections, Part II: Statistical Model of Effectiveness," M. Y. Lanzerotti Wisniewski, E. Yashchin, R. L. Franch, D. P. Conrady, G. Fiorenza, I. C. Noyan, IBM Research Report RC-22344, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, January 20, 2002.

  • "The physical design of on-chip interconnections, Part III: Statistical Model of Forecasting," M. Y. Lanzerotti Wisniewski, E. Yashchin, R. L. Franch, D. P. Conrady, G. Fiorenza, I. C. Noyan, IBM Research Report RC-22346, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, January 20, 2002.

    • The physics of computer components

  • "The physics of computer components," M. Y. Lanzerotti Wisniewski, R. N. Louie, IBM Research Report RC-22767, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, April 9, 2003.