Keynote Talk
"Expanding My Horizons"
M. Y. Lanzerotti, presented at Expanding Your Horizons Conference: Inspiring the Next Generation of Women in Math, Science, and Engineering, Cornell University, Ithaca, NY, April 23, 2005. PDF
Invited Talks
"Professional Development,"
M. Y. Lanzerotti, presented at IEEE Women in Engineering, MTA Building, New York City, NY, January 23, 2007.
"Connectivity in the Silicon Brain,"
M. Y. Lanzerotti, presented at IEEE Computer Society and IEEE Women in Engineering, Con Edison, New York City, NY, January 25, 2006.
M. Y. Lanzerotti, presented at Physics For All! Conference, Stuyvesant High School, New York, NY, November 8, 2005.
"Explore Engineering: An IBM Scientist Visits 6th Grade in Ridgefield, CT."
M. Y. Lanzerotti, presented at Ridgefield Middle School, Ridgefield, CT, December 14, 2005.
"How to Keep Your Technical Chops in Fast-Changing Fields." M. Y. Lanzerotti, presented at IEEE Spectrum Career Advancement Forum, September 20, 2005. PDF
"Connectivity in Ultralarge-scale Integrated Circuitry,"
M. Y. Lanzerotti, presented at University of New Hampshire, Durham, NH, April 25, 2005.
"A Case Study in Interconnection Design"
M. Y. Lanzerotti, presented at IBM ASICs Group, Burlington, VT, July 16, 2002.
M. Y. Lanzerotti, presented at IBM Microelectronics, Burlington, VT, April 17, 2002.
"The Physics of Computer Components".
M. Y. Lanzerotti and R. N. Louie.
M. Y. Lanzerotti, presented at the U.S. Coast Guard Academy, New London, CT, September 27, 2007. Presentation(pdf)
M. Y. Lanzerotti, presented at the Joint Spring Meeting of New York State Sections of the American Physical Society and American Association of Physics Teachers: 88th NYSS APS/AAPT Semi-Annual Symposium. SUNY Geneseo, Geneseo, NY, April 4-5, 2003. Poster Program Presentation(pdf) IBM Research Report(pdf)
M. Y. Lanzerotti, presented at IBM T. J. Watson Research Center, Local Education Outreach Science and Math Recognition Luncheon, Yorktown Heights, NY, November 8, 1999.
M. Y. Lanzerotti, presented at N.J. Governor's School in the Sciences at Drew University, Madison, NJ, August 3, 1999.
M. Y. Lanzerotti, presented at Department of Physics, Pacific Lutheran University, Tacoma, WA, February 9, 1998.
"Optical Phase Conjugation of Weak Optical Signals"
M. Y. Lanzerotti, presented at Georgia Institute of Technology, Department of Physics, October 30, 1997.
M. Y. Lanzerotti, presented at University of Illinois, Department of Physics, Champaign, IL, October 31, 1996.
M. Y. Lanzerotti, presented at Stanford University, Department of Physics, Stanford University, CA, October 28, 1996.
M. Y. Lanzerotti, presented at University of California at San Diego, Department of Physics, San Diego, CA, October 11, 1996.
M. Y. Lanzerotti, presented at University of California at Berkeley, Department of Electrical Engineering, Berkeley, CA, October 7, 1996.
M. Y. Lanzerotti, presented at Beckman Institute, University of Illinois, Champaign, IL, October 2, 1996.
M. Y. Lanzerotti, presented at IBM T. J. Watson Research Center, Yorktown Heights, NY, September 11-12, 1996.
M. Y. Lanzerotti, presented at AT&T Bell Laboratories, Holmdel, NJ, July 25, 1996.
M. Y. Lanzerotti, presented at AT&T Bell Laboratories, Murray Hill, NJ, July 23, 1996.
M. Y. Lanzerotti, presented at Cornell University, Department of Physics, Ithaca, NY, July 2, 1996.
Conference Talks
"Impact of Interconnect Length Changes on Effective Materials Properties (Dielectric Constant),"
M. Y. Lanzerotti (presenter), G. Fiorenza, R. A. Rand.
Abstract: This paper presents models and a methodology to evaluate tradeoffs between technology and design to obtain the highest frequency in ULSI design projects and quantifies the performance improvement that can be expected. With respect to the standard chip design process, it is well known in the academic community that circuits and chips are required to satisfy specific constraints, most notably the requirement that all signals must have zero slack when the transistors and wires are manufactured at some pre-specified technology node. To amortize the cost of the design process, which is time-consuming and complex, there is a need to migrate the designs to future technology nodes with minimal redesign. However, this problem and the associated implications of design migration are less well known, and at present there are no existing models to help designers evaluate whether migrated designs will operate successfully in a future technology or whether migrated designs will fail and thus cause chip failure. Thus, there is a need for research to evaluate the impact of design changes on chip performance. This paper presents a methodology to evaluate and quantify the performance impact of design changes, where we express the impact on performance as an effective change in dielectric constant in the wire environment. In this study, as in a previous study, performance estimates obtained from the model are compared with values obtained for interconnections in 18 ASIC-like control logic designs in the Instruction Fetch Unit (IFU) of the 1.3GHz POWER4 microprocessor.
2007, System-Level Interconnect Prediction
Conference (SLIP), Austin, TX. March 18, 2007. PDF
"The Physical Design of the POWER6 Microprocessor,"
Joshua Friedrich (presenter), Bradley McCredie, Norman James, Bill Huott, Brian Curran, Eric Fluhr, Gauray Mittal, Eddie Chan, Yuen Chan, Donald Plass, Sam Chu, Hung Le, Leo Clark, John Ripley, Scott Taylor, Jack DiLullo, Mary Lanzerotti.
POWER6[TM] doubles the operating frequency of POWER5[TM] at constant power, includes a scalable, high-bandwidth memory subsystem capable of supporting 128-way SMP systems, and contains mainframe-like reliability, availability, and serviceability. This 341mm2 dual-core microprocessor shown in Fig. 5.11 is fabricated in a 65nm SOI process with 10 levels of low-dielectric copper interconnects [1] and contains over 700M transistors. It operates at clock frequencies exceeding 5GHz in high-performance applications, and can also operate under 100W in power-sensitive applications.
2007, International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 11 - 15, 2007. PDF
"Modeling of Defect-Limited Yield in Semiconductor Manufacturing,"
Emmanuel Yashchin (presenter), IBM Research; Michael Baron, University of Texas at Dallas; Asya Takken, IBM Microelectronics Division; Mary Lanzerotti, IBM Research Division.
2006, International Workshop on Applied Probability (IWAP), Department of Statistics, University of Connecticut, CT, May 15-18, 2006. PDF
"Characterization of the Impact of Interconnect Design on the
Capacitive Load Driven by a Global Clock Distribution."
G. G. Lopez (presenter), G. Fiorenza, T. Bucelot, P. Restle,
M. Y. Lanzerotti. Abstract: Power reduction techniques are a
critical issue in the design of today's ULSI chips. This talk is
concerned with methods to characterize the capacitive load on the
POWER4 on-chip global clock distribution, which is a large contributor
to the overall chip power dissipation. A characterization of the
capacitive load is needed because the contributions of the on-chip
devices and interconnections are typically overestimated and are not
well understood for high performance microprocessors. One problem
that results from the lack of this information is excessively high
power dissipation in the chip global clock distribution; the global
clock distribution is over-designed and stronger than necessary to
drive the actual (lower) chip load. Information about the capacitive
load is difficult to obtain because the data volume is large, and
extracting the interconnect data is a complex task. Sophisticated
computer software is needed to extract the circuit and physical design
data for hundreds of devices and wire segments within the chip design
schedule.
This talk presents the first comprehensive characterization of the
clock load for ASIC-like control logic designs in the 1.3GHz POWER4
microprocessor core. This characterization was achieved with the use
of sophisticated software written for this study to accomplish the
task of extracting the data from these designs. Analysis of the data
shows that the wire contribution to the chip capacitive load is
significant and can increase the capacitive load of a design by 30% on
average and by as much as 130% for some designs. The results also
suggest that the wire load contribution on each metal layer can be
reduced if an alternate interconnect design style is selected. Two
alternate design styles are presented and show that a capacitive load
reduction of 8.4% to 20% is expected for each design. Extended to the
entire chip, the results show that the load reduction for the core is
expected to be as high as 10%. These values are large enough that one
alternate design style has been implemented in the design methodology
of future chips, such as the POWER5 microprocessor.
2005, Great Lakes Symposium on VLSI Design
(GLSVLSI), Chicago, IL, April 17-19, 2005. PDF
"Predicting Interconnect Requirements in Ultra-large-scale
Integrated Control Logic Circuitry." M. Y. Lanzerotti (presenter),
G. Fiorenza, R. A. Rand. Abstract: This paper presents a
comprehensive assessment of interconnect requirements in ULSI control
logic circuitry and quantifies the agreement observed (1) between
estimates and measurements of average wire-length in individual
designs in real chips, and (2) between wire-length distributions
provided by the models and wire-length distributions obtained from
measurements. In this study, actual interconnect data is measured in
ASIC-like control logic designs in the six functional units of the
1.3GHz POWER4. This paper compares interconnect measurements with
estimates for control logic in individual designs, in functional
units, and in the entire POWER4 core. The results presented in this
paper show that the estimates are typically lower than the actual
wire-length measurements. The results also show that the estimates of
the total wire-length for all of the control logic in the POWER4 agree
to within 31% of the total measured wire-length.
2005, System-Level Interconnect Prediction
Conference (SLIP), San Francisco, CA, April 2-3, 2005. PDF
"Estimating the Efficiency of Collaborative Problem-Solving, with Applications to Chip Design."
M. Y. Lanzerotti Wisniewski (presenter), E. Yashchin, R. L. Franch, D. P. Conrady, G. Fiorenza, I. C. Noyan.
Abstract: We present a statistical framework to address questions that arise in general problems involving collaboration of several contributors. One instance of this problem occurs in the complex process of designing ultralarge-scale integration semiconductor chips. In cases involving complex designs, the computer-aided design tools are unable to create designs that satisfy specified project criteria, and a number of questions arise about how to measure the effectiveness of systematic external intervention that is implemented with some supplemental algorithm. As an example, we apply the statistical framework to the problem of routing a functional unit of the IBM POWER4 microprocessor.
2003 Quality and Productivity Research Conference, IBM T. J. Watson Research Center, Yorktown Heights, NY, May 21-23, 2003.
Invited: IBM Conference on Statistics, IBM T. J. Watson Research Center, Yorktown Heights, NY, December 6, 2002.
