About me
Research Staff Member
Research lab: Watson Research Center (Yorktown)
Alexander Rylyakov is a Research Staff Member at the IBM T.J. Watson Research Center in Yorktown Heights, New York.
He received the MS degree in Physics from Moscow Institute of Physics and Technology in 1989, and the PhD degree in Physics from SUNY Stony Brook in 1997.
His main research interests are in the areas of high-speed digital and mixed-signal communication circuits.
Dr. Rylyakov has designed and tested a number of high-speed and ultra-high-speed benchmark digital circuits in CMOS, SiGe bipolar and in superconductor Josephson junction-based technologies. The highlights of that effort include a 30Gb/s demultiplexer in 0.13um CMOS, a 60Gb/s demultiplexer in 0.18um SiGe, 0.13um SiGe dividers (100GHz dynamic, 96GHz static), and a 770GHz RSFQ T-flip-flop. At the time of publication, all these circuits have established performance records in their respective technologies. The 770 GHz flip-flop still stands as the world's fastest digital integrated circuit.
Dr. Rylyakov has published research in the area of purely digital circuits with emphasis on high performance full-custom implementations. Examples of this work are a 2.3GS/s low latency 10-tap 6-bit digital FIR filter and a self-timed variable latency digital FIR filter in 0.18um CMOS. Both these circuits use dual-rail dynamic domino logic.
Presently, Dr. Rylyakov is very actively involved in the design of high-speed (in the 10Gb/s range) transcievers for wireline channel-limited communications. The main focus of that work is on filtering and various equalization techniques and on low power and small size, targeting applications with hundreds and thousands of I/O interfaces per chip. Representative results of this effort include a low power 10Gb/s transmitter with a 4-tap feed-forward equalizer (FFE) in 90nm CMOS, a 10Gb/s eye opening monitor in 0.13um CMOS, a 5mW 6Gb/s receiver with a 2-tap decision-feedback equalizer (DFE) in 90nm CMOS. There is on-going work in more advanced generations of CMOS (65nm and 45nm).
Another important area of Dr. Rylyakov's current research interests is the all-digital PLL project. The grand challenge is to implement an analog circuit with purely digital means. The main driving force behind this effort is the continuing scaling of CMOS. On one hand, scaling makes digital circuits faster and cheaper. The analog components, on the other hand, continue to suffer from various imperfections (mismatch, leakage, reduced voltage headroom, to name a few). In other words, the goal is to shift the circuit operation from voltage representation (analog) into discrete time domain (digital). One result of that effort is described in the ISSCC 2007 paper titled "A Wide Power Supply Range (0.5V—1.3V) Wide Tuning Range (500 MHz—8 GHz) All Static CMOS All Digital PLL in 65 nm SOI".
Recent and Selected Publications
"A 7.5-GS/s 3.8-ENOB 52-mW Flash ADC with Clock Duty Cycle Control in 65nm CMOS", (with H. Chung et. al.), accepted for VLSI 2009
"A 19Gb/s 38mW 1-Tap Speculative DFE Receiver in 90nm CMOS", (with D. Turker et. al.), accepted for VLSI 2009
"Bang-Bang Digital PLLs at 11 GHz and 20 GHz with sub-200-fs Integrated Jitter for High Speed Serial Communication Applications", (with J. Tierno et. al.), ISSCC 2009. (slides)
"A 136-GHz Dynamic Divider in SiGe Technology", (with E. Laskin), SiRF 2009 (slides)
"A 90-Gb/s 2:1 Multiplexer with 1-Tap FFE in SiGe Technology", (with E. Laskin), CSICS 2008 (slides)
"A Wide Tuning Range (1 GHz-to-15 GHz) Fractional-N All-Digital PLL in 45nm SOI", (with J. Tierno et. al.), CICC 2008. (slides)
"A Modular All Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS", (with J. Tierno et. al.), ISSCC 2008 (slides)
"Low-power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers operating at < 5 mW/Gb/s/link", (with C. Schow et. al.), ISSCC, JSSC 2008
"An 11 Gb/s 2.4 mW Half-Rate Sampling 2-Tap DFE Receiver in 65nm CMOS", VLSI Symposium 2007 (slides)
"A Wide Power Supply Range (0.5V—1.3V) Wide Tuning Range (500 MHz—8 GHz) All Static CMOS All Digital PLL in 65 nm SOI,” (with J. Tierno et. al.) ISSCC 2007, JSSCC 2008 (slides)
"A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decision” (with K.L.J. Wong and C.K.K. Yang), VLSI Symposium 2006, JSSC 2007. Best student paper award. (slides)
"A Low Power 10Gb/s Serial Link Transmitter in 90nm CMOS" (with S. Rylov), CSICS 2005 (slides)
"A 10Gb/s Eye Opening Monitor in 0.13um CMOS" (with B. Analui et al.), ISSCC, JSSC 2005 (slides)
"96GHz Static Frequency Divider in SiGe Bipolar Technology" (with T. Zwick), JSSC 2004 (slides)
"A 30Gb/s 1:4 demultiplexer in 0.12um CMOS" (with S.Rylov et al.), ISSCC 2003 (slides)
"A 0.18um SiGe BiCMOS Reciever and Transmitter Chipset for SONET OC-768" (with M. Meghelli et al.), ISSCC, JSSC 2003 (slides)
"100GHz dynamic frequency divider in SiGe bipolar technology" (with L. Klapproth et al.), Electronics Letters 2003.
"50Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems" (with M. Meghelli et al.), ISSCC, JSSC 2002 (slides)
"A 1.3 GSample/s 10-tap full-rate variable latency self-timed FIR with clocked interfaces" (with J. Tierno et al.), ISSCC 2002.
"A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels" (with S.Rylov et al.), ISSCC 2001.
"Rapid single flux quantum T-flip flop operating up to 770GHz" (with W. Chen et al.), Applied Superconductivity 1999.
"A fully integrated 16-channel RSFQ autocorrelator operating at 11GHz" (with D. Schneider and Yu. Polyakov), Applied Superconductivity 1999.
"Pulse jitter and timing errors in RSFQ circuits" (with K. Likharev), Applied Superconductivity 1999.
"Temperature dependence of the penetration depth of a field into a superconductor" (with G. Klimovitch and G. Eliashberg), JETP Letters 1991.
"Relaxation time of order parameter in YBaCuO single crystal" (with G. Leviev and M. Trunin), JETP Letters 1989.
Last updated 16 Apr 2009