Exploring the Architecture of a Stream Register-Based Snoop Filter
Transactions on HiPEAC: Volume 3, Issue 2, 2008.
(with M. Blumrich and A. Gara)
Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events
ISPASS- 2008 IEEE International Symposium on Performance Analysis of Systems and Software, April 2008.
(with K. Ganesan, A. Gara, M. Gschwind, J. Sexton and R. Walkup)
Design and Implementation of the Blue Gene/P Snoop Filter (presentation)
HPCA'08 The 14th International Symposium on High-Performance Computer Architecture, February 2008.
(with M. Blumrich and A.Gara)
A Performance Counter Based Workload Characterization on Bluegene/P
The 37th International Conference on Parallel Processing (ICPP-08), September 2008.
(with K. Ganesan, L. John, and J. Sexton)
Overview of the IBM Blue Gene/P project
IBM Journal of Research and Development, Vol. 52 No. 1/2, January/March 2008.
(with IBM Blue Gene team)
Improving the Accuracy of Snoop Filtering Using Stream Registers
MEDEA Workshop in conjunction with PACT 2007 Conference, September 2007.
(with M. Blumrich)
Exploiting eDRAM Bandwidth with Data Prefetching: Simulation and Measurements
ICCD 2007, XXV IEEE International Conference on Computer Design, October 2007.
(with J. Brunheroto, F. Redigolo and A. Gara)
Massively Parallel Quantum Chromodynamics
IBM Journal of Research and Development, Vol. 52 No. 1/2, January/March 2008.
(with P. Vranas, M. Blumrich, D. Chen, A. Gara, M. Giampapa, P. Heidelberger, J. Sexton, R. Soltz, and G. Bhanot)
The Blue Gene/L Supercomputer: A Hardware and Software Story
International Journal of Parallel Programming, Vol. 35, No. 3, June 2007.
(with the Blue Gene team)
The Blue Gene/L Supercomputer and Quantum ChromoDynamics
2006 Gordon Bell Prize
Supercomputing SC'06, November 2006.
(with P. Vranas, G. Bhanot, M. Blumrich, D. Chen, A. Gara, P. Heidelberger, J. Sexton)
Exploiting Workload Parallelism for Performance and Power Optimization
IEEE Micro, Vol. 26 No. 5. September/October 2006.
(with R. Walkup and A. Gara )
A Holistic Approach to System Reliability in Blue Gene
IEEE International Workshop on Innovative Architecture for Future Generation Processors and Systems, January 2006.
(with the BlueGene team)
Power and Performance Optimization at the System Level
ACM International Conference on Computing Frontiers 2005, May 2005.
(with the BlueGene team)
The Future of Supercomputing: Optimizing Performance with Power-Efficient System Design
6th International Symposium on High Performance Computing, September 2005.
BlueGene/L: Architecture, Applications, and Future Challenges
International Conference on Parallel Computational Fluid Dynamics 2005, May 2005.
Creating the BlueGene/L supercomputer from low power System-on-a-Chip ASICs
ISSCC 2005 - IEEE International Solid-State Circuits Conference, February 2005.
(with A. Bright, M. Ellavsky, A. Gara, R. Haring, G. Kopcsay, R. Lembach, J. Marcella, M. Ohmacht)
Data cache prefetching design space exploration for the BlueGene/L supercomputer
17th International Symposium on Computer Architecture and High Performance Computing, October 2005.
(with J. Brunheroto, F. Redigolo, D. Hoenicke, A. Gara)
Blue Gene/L compute chip: Memory and Ethernet subsystem
IBM Journal of Research and Development, Vol. 49, No. 2/3, March/May 2005.
(with M. Ohmacht R. A. Bergamaschi, S. Bhattacharya, A. Gara, M. E. Giampapa, B. Gopalsamy, R. A. Haring, D. Hoenicke, D. J. Krolak, J. A. Marcella, B. J. Nathanson, M. E. Wazlowski)
Blue Gene/L advanced diagnostics environment
IBM Journal of Research and Development, Vol. 49, No. 2/3, March/May 2005.
(with M. E. Giampapa, R. Bellofatto, M. A. Blumrich, D. Chen, M. B. Dombrowa, A. Gara, R. A. Haring, P. Heidelberger, D. Hoenicke, G. V. Kopcsay, B. J. Nathanson, B. D. Steinmacher-Burow, M. Ohmacht, P. Vranas)
An Efficient System-on-a-Chip Design Methodology for Networking Applications
CASES 2004 - International Conference on Compilers, Architectures and Synthesis of Embedded Systems, September 2004.
(with C. Georgiou and I. Nair)
A Programmable, Scalable Platform for Next-Generation Networking
Book Chapter, Network Processor Design: Issues and Practices, Volume 2, Morgan Kaufmann, November 2003.
(with C. Georgiou and M. Denneau)
A Programmable Scalable Platform for Next Generation Networking
2nd Workshop on Network Processors in conjunction with HPCA-9, February 2003.
(with C. Georgiou and M. Denneau)
Blue Gene: A vision for protein science using a petaflop supercomputer
IBM Systems Journal, Volume 40, Number 2, 2001.
(with the IBM BlueGene team)
FPGA Prototyping of a RISC Processor Core for Embedded Applications
IEEE Transactions on VLSI, April 2001.
(with M. Gschwind and D. Maurer)
A fuzzy RISC processor
IEEE Transactions on Fuzzy Systems, Vol. 8, 2000, pp. 781-790.
Hardware-Software Co-Design of a Fuzzy RISC Processor Design
Automation and Test in Europe DATE 98, February 1998.
(with M. Gschwind)
Design of a programmable fuzzy logic controller
AustroChip '98, October 1998.
(with C. Almeder, A. Pany and C. Troedhandl)
FPGA Rapid Prototyping of Application-Specific Processors
VHDL Forum in Europe, May 1997.
(with M. Gschwind and D. Maurer)
Efficient FPGA Design with Logic Synthesis
Electric Engineering, May 1997.
(with M. Gschwind)
An FPGA Implementation of the MIPS Instruction Set
AustroChip '97 Workshop, April 1997.
(with M. Gschwind and D. Maurer)
Implementing Fuzzy Control Systems Using VHDL and Statecharts
European Design Automation Conference EURO-DAC '96 with EURO-VHDL '96, IEEE Computer Society Press, September 1996. (with V. Hamann)
A Generic Building Block for Hopfield Neural Networks with On-Chip Learning 1996
IEEE International Symposium on Circuits and Systems, May 1996.
(with M. Gschwind and O. Maischberger)
A VHDL Design Methodology for FPGA Efficiency
1996 European Design and Test Conference, March 1996.
(with M. Gschwind)
Neural Networks for Interconnection Area Minimization
Soft Computing '96, March 1996.
(with M. Gschwind)
From High-Level Specification to Layout: A Case Study
Workshop on Design Methodologies for Microelectronics, September 1995.
(with M. Gschwind and H. Grünbacher)
A VHDL Design Methodology for FPGAs
Field-Programmable Logic and Applications -- 5th International Workshop FPL '95, Lecture Notes in Computer Science 975, Springer Verlag 1995.
(with M. Gschwind)
VHDL Synthesis for FPGAs
Third Canadian Workshop on Field-Programmable Devices, June 1995.
(with M. Gschwind)
Rapid Prototyping of a VHDL Design with FPGAs
AustroChip '95 Workshop, April 1995.
(with M. Gschwind and G. Waleczek)
RAN˛SOM: A Reconfigurable Neural Network Architecture Based on Bit Stream Arithmetic
Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, IEEE Computer Society Press, September 1994.
(with M. Gschwind and O. Maischberger)
A Fast FPGA Implementation of a General Purpose Neuron Field-Programmable Logic: Architectures, Synthesis and Applications
4th International Workshop on Field Programmable Logic and Applications, Lecture Notes in Computer Science 849, Springer Verlag, Berlin, 1994.
(with M. Gschwind and O. Maischberger)
Space Efficient Neural Net Implementation
1994 ACM Second International Workshop on Field-Programable Gate Arrays, Berkeley, CA, February 1994.
(with M. Gschwind and O. Maischberger)