- Software Transactional Memory: Why is it only a Research toy?
Calin Cascaval, Colin Blundell, Maged M. Michael, Harold W. Cain, Peng Wu, Stefanie Chiras and Siddhartha Chatterjee.
Communications of the ACM, 51(11):40-46, November 2008. Also appearing in ACM Queue 6(6).
- Compiler and Runtime Techniques for Software Transactional Memory Optimization
Peng Wu, Maged M. Michael, Christoph Von Praun, Takuya Nakaike, Rajesh Bordawekar, Harold W. Cain, Gheorghe Cascaval, Siddhartha Chatterjee, Stefanie R. Chiras, Rui Hou, Mark F. Mergen, Xiaowei Shen, Hua Yong Wang, Kun Wang and Michael Spear.
Concurrency and Computation: Practice and Experience, March 2008.
- Call-chain Software Instruction Prefetching in J2EE Server Applications
Priya Nagpurkar, Harold W. Cain, Mauricio Serrano, Jong-Deok Choi, and Chandra Krintz
16th International Conference on Parallel Architectures and Compilation Techniques (PACT) September, 2007
- A Study of Instruction Cache Performance and the Potential for Instruction Prefetching in J2EE Server Applications
Priya Nagpurkar, Harold W. Cain, Mauricio Serrano, Jong-Deok Choi, and Chandra Krintz
Tenth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-10) January, 2007
- Conditional Memory Ordering
Christoph von Praun, Harold W. Cain, Jong-Deok Choi, and Kyung Ryu
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA), June, 2006.
- Accurate, efficient, and adaptive calling context profiling
Xiaotong Zhuang, Mauricio J. Serrano, Harold W. Cain, Jong-Deok Choi
2006 Conference on Programming Language Design and Implementation (PLDI), June 2006
- Memory Ordering: A Value-Based Approach
Harold W. Cain and Mikko H. Lipasti
Proceedings of the 31st International Symposium on Computer Architecture (ISCA) , June, 2004.
Shorter version selected for IEEE Micro Special Issue (Top Picks in Computer Architecture 2004). (pdf)
- Constraint Graph Analysis of Multithreaded Programs
Harold W. Cain, Mikko H. Lipasti, and Ravi Nair
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT), September, 2003.
Longer version published in Journal of Instruction-Level Parallelism, vol. 6, April 2004. (pdf)
- Redeeming IPC as a Performance Metric for Multithreaded Programs
Kevin M. Lepak, Harold W. Cain, and Mikko H. Lipasti
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT), September, 2003.
- Verifying Sequential Consistency Using Vector Clocks
Harold W. Cain and Mikko H. Lipasti
Proceedings of the 14th Symposium on Parallel Algorithms and Architectures Revue (SPAA), August, 2002.
- Precise and Accurate Processor Simulation
Harold W. Cain, Kevin M. Lepak, Brandon A. Schwartz, and Mikko H. Lipasti.
5th Workshop On Computer Architecture Evaluation Using Commercial Workloads (CAECW), February 2002.
- Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing pdf
Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, and Mikko H. Lipasti
Proceedings of the 34th International Symposium on Microarchitecture (MICRO) , December, 2001.
- An Architectural Evaluation of Java TPC-W
Harold W. Cain, Ravi Rajwar, Morris Marden and Mikko H. Lipasti.
Proceedings of the 7th International Symposium on High-Performance Computer Architecture (HPCA), January, 2001.
- A Dynamic Binary Translation Approach to Architectural Simulation
Harold W. Cain, Kevin M. Lepak, and Mikko H. Lipasti.
Workshop on Binary Translation (WBT), October 2000 .
- A Callgraph-Based Search Strategy for Automated Performance Diagnosis .
Harold W. Cain, Barton P. Miller, Brian J.N. Wylie.
Euro-Par 2000, Munich Germany, August 2000.
Also appearing in Concurrency and Computation: Practice and Experience, 14(3): 203-217 (2002).
- Characterizing a Java Implementation of TPC-W
Todd Bezenek, Harold Cain, Ross Dickson, Timothy Heil, Milo Martin, Collin McCurdy, Ravi Rajwar, Eric Weglarz, Craig Zilles and Mikko Lipasti
3rd Workshop On Computer Architecture Evaluation Using Commercial Workloads (CAECW), January 2000. - Memory Ordering: A Value-Based Approach