As CMOS scaling becomes increasingly difficult, low-power, dense bit storage is needed for microprocessor caches. Building upon circuit-level work begun in the 1990's, the Computer Architecture department continues to make innovative contributions to next-generation caches.
Pioneering work in Embedded DRAM
Researchers in the Computer Architecture and Circuits departments at the TJ Watson center were pioneers in the area of eDRAM, or embedded, merged-logic DRAM. In 2005, Richard Matick and Stanley Schuster detailed this early process of making a deep-trench DRAM cell in the IBM logic technology process. Their paper, “Logic-based eDRAM: Origins and Rationale for Use,” is available on-line from the IBM Journal of Research and Development.
BlueGene/L
Through several generations of ASIC (bulk) technology, IBM had many OEM customers using its embedded DRAM technology. eDRAM reached the forefront for IBM's own products, however, with the BlueGene/L supercomputing system, where it was used to create a large on-chip L3 cache. In addition to a SBAC-PAD 2005 paper ("The eDRAM-based L3-cache of the BlueGene/L supercomputer procesor node"), details of this technology and implementation can be found in the IBM Journal of Research and development, in S. Iyer et al, "Embedded DRAM: Technology Platform for the BlueGene/L Chip”.
Bringing eDRAM to SOI technology
For the last several lithography generations, IBM's high-performance server processors have been made using SOI, or Silicon-on-Insulator manufacturing technology. Initial generations of embedded DRAM were made in bulk, a fundamentally different processing technology. At IEDM 2006, IBM presented its first deep-trench, SOI-based embedded DRAM cell (G. Wang et al., “A 0.127um2 High Performance 65nm SOI Based Embedded DRAM for on-Processor Applications”), followed by a presentation of a full SOI eDRAM array based on this cell, at ISSCC 2007 (J. Barth et al., “A 500MHz Random Cycle, 1.5ns-latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier").
Computer Architecture
From a computer architect's view, embedded DRAM offers an exciting opportunity for designing caches with several new dimensions of flexibility. The embedded DRAM arrays presented at ISSCC 2007 are based on a high-performance "micro-sense-amplifier" design, which brings array latency into the same order of magnitude as that of SRAM. Being much faster than prior embedded DRAM offerings, this increase in speed, along with the porting of eDRAM technology into SOI, opens the possibility for embedded DRAM use in high-performance microprocessors. Finding optimal, and beneficial, design points, however, is a delicate balance amongst cache capacity, speed, and power requirements, and embedded DRAM offers an interesting set of choices for designers traditionally offered only SRAM arrays from which to construct their caches. Work in the Computer Architecture department is truly inter-disciplinary in the eDRAM space, spanning contributions of circuit-level techniques for improving array and cache latency, to management of refresh and cache re-design to leverage higher array bandwidth.
Last updated 17 Jul 2007