Past Program, 2006

MONDAY OCTOBER 16

8:00-9:00 Registration and Breakfast

9:00-9:15 Opening Remarks

9:15-10:00 Keynote: Tilak Agerwala, VP Systems, IBM Research

Future Systems: Challenges and Opportunities

10:00-10:45 Keynote: Arvind, Massachusetts Institute of Technology

Synthesis of Parallel Programs

10:45-11:00 Break

11:00-11:45 Invited talk: Josep Torrellas, University of Illinois, Urbana-Champaign

How Micro-architects Can Help Solve the Problem of Parameter Variation

11:45-12:30 Invited talk: Doug Burger, University of Texas at Austin

Exploiting Parallelism Adaptively with Composable Cores

12:30-1:30 Lunch

1:30-3:35 Session 1: Bob Philhower, chair

1.  Assaf Shacham, Keren Bergman, Luca P. Carloni (Columbia University)

Maximizing GFLOPS-per-Watt: High-Bandwidth, Low Power Photonic On-Chip Networks

2.  Sebastian Herbert, Siddharth Garg, Diana Marculescu (Carnegie Mellon University)

Reclaiming Performance and Energy Efficiency from Variability

3.  Hui Wu, Lin Zhang, Aaron Carpenter, Alok Garg, Michael Huang (University of Rochester)

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-End Microprocessors

4.  Manu Awasthi, Rajeev Balasubramonian (University of Utah)

Exploring the Design Space for 3D Clustered Architectures

5.  Ke Meng, Russ Joseph (Northwestern University)

Physical Resource Matching Under Power Asymmetry

3:35-4:00 Break

4:00-5:45 Panel on Enabling Multi-core Technologies: From Architecture to Programming Models

Bob Blainey (IBM), Babak Falsafi (CMU), Christos Kozyrakis (Stanford), Charles Leiserson (MIT), David Padua (UIUC), Balaram Sinharoy (IBM)

Moderated by Siddhartha Chatterjee (IBM)

6:15-8:30 Dinner

Yorktown Cafeteria

TUESDAY OCTOBER 17

8:30-9:00 Breakfast

9:00-9:45 Keynote: Bijan Davari, VP Next Generation Computing Systems and Technology, IBM Fellow

Next Generation Systems: Multi-core, Flexible and Modular for the Application Optimized Integrated Solutions

9:45-10:30 Invited talk: Wen-mei Hwu, University of Illinois, Urbana-Champaign

Top Five Reasons Why Sequential Programming Models Could Be the Best Way to Program Many-core Systems

10:30-11:15 Invited talk: Beng-Hong Lim, VMware

Transforming the Computing Infrastructure with Virtualization Technology

11:30-12:45 Session 2: Michael Hind, chair

1.  Michael Noeth, Jaydeep Marathe, Frank Mueller, Martin Schulz, Bronis R. de Supinski (NCSU, LLNL)

Scalable Compression and Replay of Communication Traces in Massively Parallel Environments

2.  Chris Colonna, Aneesh Aggarwal (SUNY Binghamton)

Efficient Register Allocation

3.  Pablo Montesinos, Wei Liu, Josep Torrellas (University of Illinois, Urbana-Champaign)

Shield: Cost-Effective Soft-Error Protection for Register Files

12:45-1:45 Lunch

1:45-3:25 Session 3: Philip Emma, chair

1.  Naveen Muralimanohar, Rajeev Balasubramonian (University of Utah)

The Effect of Interconnect Design on the Performance of Large L2 Caches

2.  Major Bhadauria, Karan Singh, Sally A. McKee, Gary Tyson (Cornell University, Florida State University)

A Precisely Tunable Drowsy Cache Management Mechanism

3.  Mrinmoy Ghosh, Hsien Hsin (Sean) Lee (Georgia Tech)

DRAMdecay: Using Decay Counters to Reduce Energy Consumption in DRAMs

4.  Javi Martinez, Joseph Nayfach, Jose Renau (University of California, Santa Cruz)

Complexity Reduction through Architectural Pruning