Past Program, 2004

2004 P=ac2 Conference Program

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WEDNESDAY, OCTOBER 6 __________________________________________________________________________________________

8:15 - 8:50 WELCOMING REMARKS

Opening Address
Paul Horn, IBM Senior Vice-President, Research Division

8:50 - 10:25 Session 1: MODELING AND MONITORING

Modeling Wire Delay, Area, Power, and Performance in a Simulation Infrastructure
Hussein Azmat and Nicholas P. Carter
University of Illinois at Urbana-Champaign

Performance and Environment Monitoring for Whole-System Characterization and Optimization
Robert W. Wisniewski, Peter F. Sweeney, Evelyn Duesterwald, and Calin Cascaval
IBM T.J. Watson Research Center
Kartik Sudeep
IBM Austin Research Lab
Matthias Hauswirth
University of Colorado at Boulder
Reza Azimi
University of Toronto

HeapMon: a Low Overhead, Automatic, and Programmable Memory Bug Detector
Rithin Shetty, Mazen Kharbutli, Yan Solihin Milos Prvulovic
North Carolina State University Georgia Institute of Technology

10:55 - 12:30 Session 2: POWER AND THERMAL ISSUES

Evaluating the Thermal Efficiency of SMT and CMP Architectures
Yingmin Li and Kevin Skadron
CS Dept, University of Virginia
Zhigang Hu
IBM T.J. Watson Research Center
David Brooks
EECS Dept, Harvard University

TEAPC: Adaptive Computing and Underclocking in a Real PC
Augustus K. Uht and Richard J. Vaccaro
Microarchitecture Research Institute, ECE Department University of Rhode Island

Reducing Static Power Dissipation in Region-Based Caches
Michael J. Geiger Gary S. Tyson
Advanced Computer Architecture Lab Department of Computer Science University of Michigan Florida State University

1:45 - 2:50 Session 3: DYNAMIC VOLTAGE SCALING EDF-DVS

Scheduling on the IBM Embedded PowerPC 405LP
Aravindh V. Anantaraman, Ali El-Haj Mahmoud, Ravi K. Venkatesan, Yifan Zhu and Frank Mueller
North Carolina State University

A Rate Matching-based Approach to Dynamic Voltage Scaling
David A. Biermann, Rajit Manohar, and Gun Sirer
Cornell University ____________________________________________________________________________________________
THURSDAY, OCTOBER 7 ____________________________________________________________________________________________

9:00 - 10:05 Session 4: PROGRAMMABLE HARDWARE

Application Specific Instruction Set Synthesis to Reduce Instruction Cache Power in Embedded Processors
Allen Cheng
Advanced Computer Architecture Lab, Univ of Michigan Department of Computer Science
Gary Tyson
Florida State Univ

Programmable Hardware for Deep Packet Filtering on a Large Signature Set
Young H. Cho and William H. Mangione-Smith
UCLA Department of Electrical Engineering 10:05 - 10:30 Break

10:30 - 11:35 Session 5: MEMORY WALL

Braids and Fibers: Language Constructs with Architectural Support for Adaptive Response to Memory Latencies
David F. Bacon and Xiaowei Shen
IBM T.J. Watson Research Center

Runtime Register Allocation
Kemal Ebcioglu and Vivek Sarkar
IBM T.J. Watson Research Center
Kartik Agaram
University of Texas at Austin 11:35 - 1:00 Lunch: Cafeteria Annex

1:00 - 2:00 KEYNOTE ADDRESS

Bluegene
George Chiu, Senior Manager, Advanced Server Hardware Systems
Manish Gupta, Senior Manager, Emerging System Software

2:00 - 3:00 Break / Bluegene Lab Tours

 

3:00 - 4:35 Session 6: CLUSTERED MICROARCHITECTURE

Demand-Only Broadcast: Reducing Register File and Bypass Power in Clustered Execution Cores
Mary D. Brown and Yale N. Patt
Electrical and Computer Engineering, The University of Texas at Austin

Dynamically Matching ILP Characteristics Via a Heterogeneous Clustered Microarchitecture
Lei Chen and David H. Albonesi
Dept of Electrical & Computer Eng, Univ of Rochester
Stephen Dropsho
Dept of Computer Science, Univ of Rochester

A Communication-Centric Approach to Instruction Steering for Future Clustered Processors
Ashok Jagannathan, Glenn Reinman, Yuval Tamir, and Jason Cong
University of California, Los Angeles __________________________________________________________________________________________

6:00 - P=AC2 Dinner Banquet at Lexington Square Café, Mount Kisco __________________________________________________________________________________________

FRIDAY, OCTOBER 8 _________________________________________________________________________________________

9:00 - 10:35 Session 7: REDUCING MICROARCHITECTURAL ACTIVITY

Decomposing the Load-Store Queue by Function for Power Reduction and Scalability
Lee Baugh and Craig Zilles
University of Illinois at Urbana-Champaign

The Calm Before the Storm: Reducing Replays in the Cyclone Scheduler
Yong-Xiang Liu, Anahita Shayesteh, and Glenn Reinman
University of California, Los Angeles
Gokhan Memik
Northwestern University Selective

Writeback: Increasing Processor Performance and Energy-Efficiency
Deniz Balkan, Oguz Ergin, Dmitry Ponomarev, and Kanad Ghose
State University of New York at Binghamton 10:35 - 11:00 Break

11:00 - 12:35 Session 8: CHIP MULTIPROCESSORS

Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors
Jian Li and Jose Martinez Cornell University

Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
Dhruba Chandra, Fei Guo, Seongbeom Kim, and Yan Solihin
North Carolina State University

Fair Caching in a Chip Multi-Processor Architecture
Seongbeom Kim, Dhruba Chandra, and Yan Solihin
North Carolina State University 12:35 - 2:00 Lunch: Cafeteria Annex

2:00 - 3:00 KEYNOTE ADDRESS: IBM INTERNAL SESSION

Ideas for High Performance Linear Algebra Software
Fred G. Gustavson IBM Research: Optimization and Mathematical Software