2005 P=ac2 Conference Program
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WEDNESDAY, SEPTEMBER 28
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Opening Address
Tilak Agerwala
IBM Research VP of Systems
Alan Gara on Bluegene
A Case for Increased Operating System Support in Chip Multi-Processors
David Nellans, Rajeev Balasubramonian, Erik Brunvand
University of Utah
Conditional Memory Ordering
Christoph von Praun and Harold W. Cain
IBM T.J. Watson Research Center
Architecture Cloning For PowerPC Processors
Edwin Chan, Raul Silvera, Roch Archambault
IBM Toronto Labs
A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads
Mingliang Wei+, Marc Snir+, Josep Torrellas+, R. Brett Tremaine*
+ = Univ of Illinois at Urbana-Champaign * = IBM T.J. Watson Research Center
A Prediction Model for Alternative Cache Replacement Policies
Fei Guo and Yan Solihin,
North Carolina State University
Software-Hardware Cooperative Memory Disambiguation
Ruke Huang and Michael Huang
University of Rochester
Scalable, Low-Complexity Instruction Schedulers for SMT Processors
Joseph J. Sharkey, Deniz Balkan, Dmitry V. Ponomarev
State University of New York at Binghamton
A New Approach to Thread Extraction for General-Purpose Programs
Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August
Princeton University
POSH: A Profiler-Enhanced TLS Compiler that Leverages Program Structure
Wei Liu+, James Tuck+, Luis Ceze+, Karin Strauss+, Jose Renau*, Josep Torrellas+
+ = Univ of Illinois at Urbana-Champaign, * = Univ of California at Santa Cruz
On the Energy Effectiveness of If-conversion in Superscalar Microprocessors
Eric Zimmerman, Craig Zilles
University of Illinois at Urbana-Champaign
Hybrid Leakage and Voltage Reduction under EDF Scheduling
Yifan Zhu Frank Mueller
North Carolina State University
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THURSDAY, SEPTEMBER 29 (IBM Day – OPEN TO THE
PUBLIC)
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Peter Hofstee on Cell
Compiling for the Heterogeneous Parallelism of the Cell Architecture
Kevin O’Brien, Kathryn O’Brien, Alexandre Eichenberger, and Michael Gschwind
Bruce D'Amora on Cell Programming Models, Graphics and Visualization. Introduction
to Demos.
Cell
Charles Webb on zSeries Mainframes
Balaram Sinharoy on Power5 / PERCS
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FRIDAY, SEPTEMBER 30
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Highly Accurate Power Modeling Method for SRAM Structures with Simple Circuit
Simulation
Xiaoyao Liang, David Brooks
Harvard University
Improving Adaptive Cache Leakage Reduction Techniques with Line Buffers
Gurhan Kucuk+, Kanad Ghose*
+ = Yeditepe University * = State University of New York at Binghamton
Using Rotary Clock For Low-Power Clock Distribution
Zhentao Yu, Xun Liu North Carolina State University
Simple Is Better: Keeping Elmore Delay In Repeater Insertion
Yuantao Peng, Xun Liu
North Carolina State University
DLL-Conscious Instruction Fetch Optimization for SMT Processors
Fayez Mohamood, Mrinmoy Ghosh, Hsien-Hsin S. Lee
Georgia Institute of Technology
Loop-based iTLB Resizing for Energy Reduction
Bramha Allu, Wei Zhang
Southern Illinois University, Carbondale
Improving the Energy and Execution Efficiency of a Small Instruction Cache
by Using an Instruction Register File
Stephen Hines, David Whalley, Gary Tyson
Florida State University
Compiler-guided Register Reliability Improvement Against Soft Errors
Yun Yan, Wei Zhang
Southern Illinois University, Carbondale
Instruction Error Rate Modeling for High Performance Microprocessors
Aneesh Aggarwal
State University of New York at Binghamton
Optimal Resource Allocation for Concurrent Error Detection Techniques in
High Performance Microprocessors
Sumeet Kumar, Aneesh Aggarwal
State University of New York at Binghamton
Reliability Metrics for Processor and System Design: Insights and Pitfalls.
Panelists:
Prof. Jacob Abraham University of Texas
Prof. Sarita Adve University of Illinois at Urbana-Champaign
Dr. Phil Emma IBM T. J. Watson Research Center
Dr. Shubu Mukherjee Intel
Ms. Lisa Spainhower IBM Systems and Technology Group