Fabrication on a standard 200mm CMOS line
 Processed 200mm SOI wafer (click on the image to enlarge) |
We aimed at development of nanophotonic technology that is compatible with CMOS fabrication line. If this can be proved possible then development of nanophotonic integrated circuits, being fully compatible with microlelectronics manufacturing, might result in realization of massively parallel ultra-compact all-optical devices integrated with control electronics on a chip-scale level.
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Photonic layer fabrication
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Animation of a process flow (Right mouse click to control the movie) |
SOI wafers Devices were patterned on 200 mm SOI Unibond wafers manufactured by SOITEC with 220 nm of lightly p-doped Si on a 2µm BOX layer. The thick oxide serves to optically isolate the circuit from the substrate, reducing losses due to substrate leakage. CVD oxide deposition A 50 nm thick oxide was deposited on the wafers via low pressure chemical vapor deposition to act as a hard mask for subsequent etching. First lithography step The PhC waveguides, strip waveguides and silicon taper of the fiber coupler were defined in one step by electron beam lithography using Leica’s VB6-HR commercial 100 keV system. The photonic crystal patterns were routinely over-exposed to smooth out the effects of fracturing circles into polygons for pattern writing. Two-step etch The exposed wafers containing over one thousand devices were etched in a standard 200mm CMOS line at IBM Watson Research Center. The resist pattern was transferred to the oxide hard mask using a CF4/CHF3/Ar chemistry. The resist was then removed and the patterned oxide mask transferred to the Si layer with an HBr-based etch. Sidewall angles close to 90? were obtained and sidewall rms roughness is measured with an AFM to be 1.2nm with correlation length 60nm. Second lithography for membrane definition A second lithography step is required to mask the strip waveguides and coupler regions to protect them from being underetched during BOE etching of the BOX layer for definition of the PhC membranes Third lithography for fiber couplers A final lithography step defined the epoxy polymer for the fiber coupler. Individual samples containing ~ 40 devices were then cleaved on each side to enable edge coupling. Since the refractive index (~1.58) of the epoxy polymer we used is higher than the underlying oxide the polymer waveguide by itself can support waveguiding. Extending the polymer waveguide lengthwise past the vertex of the taper provides significantly relaxed cleaving tolerances. |
Electric layer fabrication
Process flow for active nanophotonic circuit (click on the image to enlarge) |
Process flow for fabricating the active Mach Zehnder Interferometer. 1. 200mm Unibond SOI wafers (SOITEC) with 340nm thick silicon and 2µm buried oxide (BOX). The wafers have <100> orientation and were doped to approximately 10Ocm. Top silicon layer is thinned to 223nm by oxidation and oxide removal. A 50nm thick SiO2 layer is deposited on top by chemical vapour deposition that is used subsequently as an etch mask. 2. Optical waveguides are defined using electron beam lithography. The Leica VB6 tool at 100kV is used to expose a positive chemically amplified resist. 3. A two stage etch is firstly open the SiO2 hard mask using a CF4/CHF3/Ar/ chemistry. Then the resist is stripped and the silicon layer is etched with an oxide hard mask using a HBr chemistry. 4. To reduce the resistance of the integrated micro-heaters the PhC waveguides in the MZI are doped with Boron to ~ 1017 using ion implantation. A thick resist is used as a mask and an optical exposure performed to open the desired window. 5. Low resistance lateral ohmic contacts are created as in the previous step but this time boron doped to 1020. The devices are then annealed to activate the dopants at 1000?C for 5 seconds. 6. Another optical lithography step is performed to open up the contact region for nickel metal deposition (after first removing any surface oxide layer). 7. Nickel lift-off is performed, followed by a standard silicidation anneal to form NiSi. 8. Optical lithography is used to define windows in a resist over the PhC waveguide region. The BOX is then etched away by a buffered oxide etch to form membrane structures. 9. E-beam lithography was lastly performed to define fibre couplers in a photo-exposable polymer to ensure efficient coupling of light from an external fibre source. 10. Devices were cleaved for measurement. |