|
1. Could you give a brief overview of your research? 2. What is the motivation of building on-chip optical buffers? 3. Could you describe your demonstration? 4. What are the important numbers demonstrated in your device? 5. Where and how was the device fabricated? 6. How is your demonstration compared to previous results in optical buffering? 7. What were the challenges in this project? 8. Can this device be used in practical optical interconnects? 9. What is the time frame of realistic applications of on-chip interconnect devices? 10. What are the next steps? 1. Could you give a brief overview of your research? We are exploring the limits of photonic device scaling. In other words we are exploring how small such devices can be made. This is very interesting question from a research point of view, but also it is of great practical importance. If our goal is to integrate large number of optical devices on a microprocessor chip then miniaturization is a key here. At the same time we are exploring the integration of optical and electrical circuits on the same silicon chip using the same processing steps that are used for manufacturing of microprocessors. In general the broad goal of our research is to build a photonic device toolbox containing a variety of devices such as modulators, filters, WDM devices, detectors, etc. By scaling the photonic devices and integrating them with CMOS electronics, finally, we want to build on-chip optical networks. The demonstrated optical buffering device is just one of the photonic devices needed for such a complete toolbox. 2. What is the motivation of building on-chip optical buffers? Optical buffering can be used for example to help directing the busy information traffic on a chip and to avoid traffic congestion. In any network, one of the problems is signal congestion at the switching nodes that occurs for example when two data streams are arriving at the switch at the same time. Without optical buffer, the buffering has to be realized in electronic domain. In this case, optical signals have to be converted into electrical signals and stored in electrical memories for certain time, after which they are converted back to optical domain using lasers. However such a solution is almost impossible for on-chip applications because thousands of detectors and lasers would be required that is not easy to fit into very small chip area. For on-chip networks, buffering directly in optical domain has obvious advantages of simplicity, power and cost efficiency. 3. Could you describe your demonstration? Buffering of optical signals itself is a very easy task. If we let the optical signal pass through a long optical fiber, we can achieve large time delay. We can even coil a long fiber into a relatively small device. However such a device would be most certainly much larger than the whole area of a microprocessor chip. To be viable for on-chip applications optical buffers should be extremely small – ideally of the order of CMOS electronic circuits themselves. However this is exactly the challenge here. The basic building block in our demonstration, silicon submicron photonic wire waveguide, has a cross section of below 0.1um2. Optical delay can be realized just using such waveguide along, however we would need about 7cm of such a waveguide. Here, we used optical micro-resonators based on these waveguides to further decrease the device area since footprint is very, very expensive. By bending such a photonic waveguide and forming a micro-ring, light can propagate multiple times in the ring when light wavelength is tuned to the ring resonance, and hence delay can be significantly enhanced. 4. What are the important numbers demonstrated in your device? There are four important metrics to consider here: total time delay, bandwidth, loss, and device area. Total delay and bandwidth are usually going side by side – the larger the delay the smaller the bandwidth. So it is usually the combined metrics – delay-bandwidth product - that is frequently considered. Delay –bandwidth product is also called fractional delay, or delay in the units of bits that is possible to store simultaneously in a given delay line. We demonstrated here 10 bits delay on a silicon chip that is a record number to the best of our knowledge. We used up to 100 low-loss micro-rings with moderate quality factors to achieve a balance when optimizing all these metrics. 5. Where and how was the device fabricated? The device was fabricated on the standard CMOS fabrication line at the IBM Watson Research Center in Yorktown Heights. Standard fabrication tools and processing steps utilized in front-end CMOS fabrication are used. Since eventually our goal is to integrate CMOS electronics with photonics, CMOS compatibility is very important. Hence, we use only CMOS fabrication line to make our devices to ensure the compatibility. We did not modify CMOS processing. Fortunately, in CMOS electronics, people are already dealing with a transistor gate length in the order of tens of nanometer. To make 100 rings working together in-tune, we need the control of a waveguide width, waveguide surface roughness, and micro-ring perimeters in the nanometer range. This corresponds to variations of only a few silicon atomic layers. We are indeed in the NANO-photonics domain. Fortunately, by using the advanced CMOS tools, we are able to achieve these tight requirements. 6. How is your demonstration compared to previous results in optical buffering? Except showing record long fractional delays of 10 bits on a silicon chip one of the major advantages of our demonstration is extremely small device area. The device demonstrated in this paper has a footprint as small as 0.03mm2. This is a direct result of utilizing the nanophotonic waveguides. We used photonic wire waveguide which has smaller than 0.1um2 cross-section and very high index contrast between Si and air or oxide cladding. As a result, we can bend such waveguide at a radius of of the order of just a few microns, while the loss per 90 degree bend can be as small as 0.004dB. Hence, we can make rings with such a small radius while keep the losses very small. 7. What were the challenges in this project? The most challenging and interesting part in this project is to understand the physics of this deeply scaled novel nano-photonic system. Scaling the photonics to diffraction limit in such high index contrast system leads to a whole variety of interesting unexplored phenomena. 8. Can this device be used in practical optical interconnects? We have demonstrated optical storage of 10 bits. This is enough to encode one ASCII character. However to make an optical buffer useful for on-chip optical networks the whole packets of optical signals with many words encoded there should be buffered. We would need to delay at least hundreds or even thousands of bits depending on specific network architecture. We still have a long way to go and the current device is just a first step along this road. However, it shows the huge potential of on-chip silicon photonics. Up to 100 resonators working together in-tune with each other is a very promising demonstration. 9. What is the time frame of realistic applications of on-chip interconnect devices? There is definitely a long way to go and currently this is still a long-term research project. A reasonable estimation would be somewhere in 10-15 years range when we can expect optics would appear on a microprocessor chip. However, some specialized silicon-based photonic devices integrated with CMOS electronics can go to the market even earlier in a shorter term, as for example components for telecommunications. Several companies are currently working in this particular area and they are making a very good progress. 10. What are the next steps? Next obvious step is to increase the buffering capacity to be able to store hundreds of bits. Currently this is limited by relatively large 20dB losses that are accumulated in a delau line. So we plan to decrease the loss numbers even further. Another avenue we are planning to pursue is to achieve electrical tunability of a delay time by applying electrical current to nanophotonic waveguide. This would allow to actively tune and manipulate optical signals with electrical input. |
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
