We have developed a new method for building nanocrystal FLASH memory devices that achieves precise control of nanocrystal size and position. Nanocrystal dimensions are templated by a self-assembled polymer film, providing a manufacturable solution to achieving uniformly-sized and –spaced nanocrystals. The size tunability of self assembled polymer domains also offers a route to device scaling. This work generated extensive external media attention including coverage in the New York Times, the Wall Street Journal, AP, Reuters, C/NET, the Boston Globe, and Scientific American.
For more information relating to this project, see
IBM Demos New Nanotechnology Method
IBM Nanotechnology Announcement
Schematic of nanocrystal FLASH
memory transistor
memory transistor
nanometers in diameter and are spaced 40 nanometers apart.
(b) Step 2: IBM used the polymer material as a stencil to reproduce the nanoscale pattern in silicon dioxide, which is more rugged than the polymer and able to withstand higher temperatures. At this stage the polymer material is completely removed.
(c) Step 3: A combination of depositing silicon material and etching leaves silicon nanocrystals embedded within the 20 nanometer regions defined originally by the self assembled polymer.
(d) Dimensions of the hexagonal pattern of the initial polymer (dotted curve) are maintained throughout, as shown by the histogram of the final silicon nanocrystal dimensions (solid curve). The grey curve represents the dimensions of the hexagonal pattern at an intermediate process step.
Schematic representation of nanocrystal memory device. Silicon nanocrystal arrays are formed between the device polysilicon gate and silicon substrate, and are electrically-isolated by control- and program-oxides. The nanocrystal dimensions and positions in our device are defined using self assembly.
High-resolution scanning electron microscope image of nanocrystal FLASH memory device. Arrays of uniformly-sized 20 nanometer diameter silicon nanocrystals (patterned using self assembly) are embedded between the device gate and silicon substrate. The device operates as a memory by storing charge in the nanocrystals.