"Scalable Liveness Checking via Property-Preserving Transformations"
J. Baumgartner and H. Mony,
Design Automation and Test in Europe, 2009.
[pdf]
"Speculative-Reduction based Scalable Redundancy Identification"
H. Mony, J. Baumgartner, A. Mishchenko and R. K. Brayton,
Design Automation and Test in Europe, 2009.
[pdf]
"Optimal Constraint-Preserving Netlist Simplification"
J. Baumgartner, H. Mony and A. Aziz,
Formal Methods in Computer-Aided Design, 2008.
[pdf]
"Invariant Strengthened Elimination of Dependent State Elements"
M. L. Case, A. Mishchenko, R. K. Brayton, J. Baumgartner and H. Mony,
Formal Methods in Computer-Aided Design, 2008.
[pdf]
"Merging Nodes Under Sequential Observability"
M. L. Case, V. N. Kravets, A. Mishchenko and R. K. Brayton,
Design Automation Conference, 2008.
[pdf]
"Formal Verification of Partial Good Self-Test Fencing Structures"
A. Seigler, G. V. Huben and H.Mony,
Formal Methods in Computer-Aided Design, 2007.
[pdf]
"Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning."
J. Baumgartner,
T. Gloekler,
D. Shanmugam,
R. Seigler,
G. V. Huben,
H. Mony,
P. Roessler, and
B. Ramanandray,
Formal Methods in Computer-Aided Design, San Jose, CA. November 2006.
[pdf]
"Scalable Sequential Equivalence Checking across Arbitrary Design Transformations."
J. Baumgartner, H. Mony, V. Paruthi, R. Kanzelman and G. Janssen,
International Conference on Computer Design, San Jose, CA. October 2006.[pdf]
"Automatic Verification of Fused-Multiply-Add FPUs."
C. Jacobi, K. Weber, V. Paruthi, and J. Baumgartner,
Design Automation and Test in Europe, 2005. [pdf]
"Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies."
J. Baumgartner and H. Mony,
Correct Hardware Design and Verification Methods, 2005.
[pdf]
"Exploiting Constraints in Transformation-Based Verification."
H. Mony, J. Baumgartner and A. Aziz,
Correct Hardware Design and Verification Methods, 2005.
[pdf]
"Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring,
and Case Splitting."
V. Paruthi, C. Jacobi and K. Weber,
Correct Hardware Design and Verification Methods, 2005.
[pdf]
"Scalable Compositional Minimization via Static Analysis."
F. A. Zaraket, J. Baumgartner and A. Aziz,
International Conference on Computer-Aided Design, 2005.
[pdf]
"Exploiting Suspected Redundancy without Proving It"
H. Mony, J. Baumgartner, V. Paruthi, R. Kanzelman,
Design Automation Conference , 2005. [pdf]
"Scalable Automated Verification via Expert-System Guided Transformations."
H. Mony, J. Baumgartner, V. Paruthi, R. Kanzelman and A. Kuehlmann,
Conference on Formal Methods in Computer-Aided Design, 2004.
[pdf]
"Enhanced Diameter Bounding via Structural Transformation."
J. Baumgartner and A. Kuehlmann,
Design Automation and Test in Europe, 2004.
[pdf]
"An Abstraction Algorithm for Verification of Level-Sensitive Latch-Based Netlists."
J. Baumgartner, T. Heyman, V. Singhal, and A. Aziz,
Journal of Formal Methods in System Design, Volume 23, pp. 39-65, 2003.
[pdf]
"Robust Boolean Reasoning for Equivalence Checking and Functional
Property Verification."
A. Kuehlmann, V. Paruthi, F. Krohm and M.K. Ganai,
IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, Volume 21, pp. 1377-1394, December 2002.
[pdf]
"Property Checking via Structural Analysis."
J. Baumgartner, A. Kuehlmann, and J. Abraham,
Conference on Computer-Aided Verification, 2002.
[pdf]
"Circuit Based Boolean Reasoning."
A. Kuehlmann, M.K. Ganai, and V. Paruthi,
Design Automation Conference, 2001.
[pdf]
"Design of a Pointerless BDD Package."
Geert Janssen,
International Workshop on Logic & Synthesis, 2001.
[pdf]
"Transformation-Based Verification Using Generalized Retiming."
A. Kuehlmann and J. Baumgartner,
Conference on Computer-Aided Verification, 2001.
[pdf]
"Min-Area Retiming on Flexible Circuit Structures."
J. Baumgartner and A. Kuehlmann,
International Conference on Computer-Aided Design, 2001.
[pdf]
"An Abstraction Algorithm for Verification of Generalized C-Slow Designs."
J. Baumgartner, A. Tripp, A. Aziz, V. Singhal, and F. Andersen,
Conference on Computer-Aided Verification, 2000.
[pdf]
"Equivalence Checking combining a Structural SAT-solver, BDDs and
Simulation."
V. Paruthi and A. Kuehlmann,
International Conference on Computer Design, 2000.
[pdf]
"On-the-Fly Compression of Logical Circuits."
M.K. Ganai and A. Kuehlmann,
International Workshop on Logic & Synthesis, 2000.
[pdf]
"Model Checking the IBM Gigahertz Processor: An
Abstraction Algorithm for High-Performance Netlists."
J. Baumgartner, T. Heyman, V. Singhal, and A. Aziz,
Conference on Computer-Aided
Verification, 1999. [pdf]
"Equivalence Checking using Cuts and Heaps."
A. Kuehlmann and F. Krohm,
Design Automation Conference, 1997.
[pdf]
"The Use of Random Simulation in Formal Verification."
F. Krohm, A. Kuehlmann, and A. Mets,
International Conference on Computer Design, 1996.
[pdf]
"On Invariants to Characterize the State Space for Sequential Logic Synthesis and Formal Verification Invariant-Strengthened Elimination of Dependent State Elements"
Michael L Case,
PhD Thesis. The University of California, Berkeley, CA, 2009.
[pdf]
"Sequential Redundancy Identification using Transformation-Based Verification"
Hari Mony,
PhD Thesis. The University of Texas, Austin, TX, 2008.
[pdf]
"Automatic Structural Abstraction Techniques for Enhanced
Verification."
J. Baumgartner,
PhD Thesis. The University of Texas, Austin, TX, 2002.
[pdf]