This research group focuses on exploration of the fundamental design principles that govern the performance of computer systems using both analytical tools, and detailed simulations.
Innovations from our research are applied to the design of the system Z processor core, and the memory subsystem. Some of the research topics explored are highlighted below.
A new method of obtaining, and displaying information on the detailed operation of a pipelined processor has been developed. It allows for the visualization of the costs, and benefits of various processor operations, such as cache misses, trailing edge effects, and prefetching. In particular it allows us to determine when costs overlap, reducing the penalty, or when benefits overlap, reducing their efficacy. This tool is leading to advances in processor design.
An Analysis of the Effects of Miss Clustering on the Cost of a Cache Miss
T. R. Puzak, A. Hartstein, P. G. Emma, V. Srinivasan, J. Mitchell,
In the Proceedings of the 4th conference on computing frontiers, 2007.
A statistical theory of cache operation has been worked out, which shows that cache misses depend on cache size by a negative inverse power law in agreement with observation. The theory shows that this law arises from the temporal dependence of cache references. This understanding leads to an accurate analytical model of cache performance, and to a theory of the optimal memory hierarchy for a processor.
Cache Miss Behavior, is it √2?
A. Hartstein, V. Srinivasan, T. R. Puzak, P. G. Emma,
In the Proceedings of the 3rd conference on computing frontiers, 2006, Pages: 313 - 320.
This work provides a robust methodology to analyze the effectiveness of prefetches in the presence of realistic bus bandwidth, and latencies at different levels of the memory hierarchy. A cycle accurate model developed for this work allows exploration of the benefits of any arbitrary prefetch algorithm by suitably setting the timeliness, accuracy, and coverage parameters.
Exploring the Limits of Prefetching
P.G. Emma, A. Hartstein, T.R. Puzak, V. Srinivasan,
IBM Journal of Research and Development, Volume 49 , Issue 1 (January 2005) , Pages: 127 - 144.
An analytical theory of the optimal pipeline depth for a microprocessor has been developed and verified with simulations. The theory can give results dependent only on a performance metric or a combined power performance metric. This allows us to readily choose an initial FO4 design point early in the design process, and study the trade-offs inherent in any real design problem.
The Optimum Pipeline Depth of a Processor
A. Hartstein, T. R. Puzak,
In the Proceedings of the 29th annual international symposium on computer architecture, 2002, Pages: 7 - 13.
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Last updated 10 Mar 2008