Early in the next century, the rapid shrinking of transistors --
which has led to a doubling of computer performance every three years
-- will come to an end. What then?
In Brief:
As IBM scientists contemplate the lower size limits of transistors, they are trying
to extend the process of miniaturization as far as
possible. Innovations like X-ray lithography, combined with new device designs and
materials, can help.
Steady, exponential increase in the performance of integrated circuits has been
a reliable feature of the computer industry for the past 40 years. After a period of even
faster growth in the 15 years following the invention of the integrated circuit in 1959,
the industry settled into a pace of a new generation of circuits every three years.
Each successive generation of circuits has had more than twice the speed, four times
the number of transistors and four times the memory of the previous one. This phenomenon,
broadly known as Moore's Law, has made computers faster and abler every year, so that
today's desktops pack more power than yesterday's supercomputers, at a small fraction of the cost.
But all good things must come to an end. No one believes that transistors based on the existing technology,
termed CMOS (for complementary metal-oxide semiconductor), can shrink without limit. At some point,
this steady progress will have to slow and finally stop, or continue only with a fundamentally different technology.
The key questions are: What and where are the limits? How can they be pushed back as far as possible? And when will
they begin to hamper CMOS development?
Along with much of the industry,
IBM researchers have been focusing on these questions with growing urgency.
While previous predictions of when limits would be reached have proved overly pessimistic,
there is a growing consensus that the present pace cannot be sustained for another 20 years.
Nor will it come to a screeching halt. Rather, beginning perhaps 10 years from now, or even sooner,
the slope of progress will moderate and the industry will have to advance in a lower gear.
But between now and then, a lot of work will be done in an effort to postpone that slowdown as long as possible.
First, new lithographic methods are needed to shrink the lines
and patterns that define circuits. IBM has focused on extending conventional optical lithography
while at the same time pioneering a more advanced technique using X-rays instead of ultraviolet light.
Second, device design must change so that as devices shrink, unintended electrical effects do not disrupt
circuit function. IBM is addressing these issues by developing silicon-on-insulator technology and novel
device structures such as the double-gate transistor, which can be scaled to the smallest size possible.
Finally, memory devices have to shrink in tandem with circuits, requiring the use of different physical principles
-- some based on novel applications of quantum theory -- for storing information.
Defining the Limit
So, where are the limits today? The first place to look is in the process of putting the patterns on the chips.
Lithography. This has long been the technological driver of shrinking circuits,
since the capacity to create finer and finer features for transistors has to exist before the problem
of designing such tiny circuits can be addressed in practice. Lithography involves shining light or other
radiation through a mask that exposes only the parts of a wafer that are to be etched away. The wavelength
of the radiation determines how fine a line can be created with this process. It is impossible to define
features that are significantly smaller than one wavelength. As a result, as the industry has advanced,
lithography has moved to steadily shorter wavelengths of light
(see "Sharpening Lithography," below).
Quantum tunneling. Making transistors smaller is only half the battle. They have to work,
and work faster, for the improvement trend to continue. You cannot simply shrink transistors and expect them to
function properly. In the early 1970s, IBM Fellow Robert Dennard, the inventor of dynamic random access memory (DRAM),
and his colleagues determined that transistors had to follow scaling laws that dictate how various transistor parameters
must change as linear dimensions shrink.
Two limits on the horizon will have a huge impact on future progress in CMOS.
The first arises because of the scaling law that requires a reduction in the thickness
of the silicon oxide that insulates the gate (the part of the transistor whose voltage level
is used to turn the transistor on and off). As the oxide is thinned to only a few atomic layers,
electrons will begin to leak through it by the process of quantum tunneling. In practice,
that means that the gate oxide should have a thickness of at least 2 nanometers (billionths of a meter),
or about four layers of atoms.
This limitation affects other dimensions of the transistor through various scaling laws.
In particular, the length of the channel under the gate is limited to about 50 nm.
Such channel lengths will be possible once lithographic advances shrink line widths to 100 nm,
says Yuan Taur, manager of exploratory logic devices at IBM's Thomas J. Watson Research Center.
That should happen around eight years from now, in 2006, according to the National Technology Roadmap
for Semiconductors (NTRS), an industrywide projection of future progress, which assumes Moore's Law will continue to hold.
One way around this gate-oxide limitation might be to replace the silicon oxide with another material that can store more charge for a given thickness of material, which is essential for memory cells. "If we go to silicon nitride, we could have twice the thickness for the same line width, which means the capacitance remains the same but the chance of tunneling is reduced," comments Taur. However, tunneling is somewhat easier through silicon nitride, so the net gain is about 50 percent (relative to silicon oxide), which might allow a line width of 50 nm.
Supply voltage. One of Dennard's most important scaling laws is that the strength of the electric field within the transistor should be maintained as a constant, meaning that the gate voltage used in switching would fall in direct proportion to linear dimensions, since field strength is voltage divided by distance.
Dennard and his colleagues realized, however, that the amount that the gate voltage must be increased or decreased to turn off a transistor is set by the thermal energy of electrons. Because that energy depends solely on the temperature, it does not change with scaling. That limits the lowest threshold voltage -- the minimum required to turn on the transistor -- to about 0.3 volt. If the supply voltage is lowered with respect to a nearly constant threshold voltage, the transistor slows down. Since increased speed is the major impetus for shrinking transistors, the supply voltage has not been scaled down in proportion to the channel length.
Nevertheless, supply voltage has been scaled down and must continue to drop. Otherwise the electric field in the transistor would grow dangerously strong. "When the field strength in a transistor becomes high enough, a number of deleterious effects can occur," explains Tak Ning, an IBM Fellow at Watson. For example, an excessively high field will rip electrons from atoms and free them to move, creating an undesirable and often uncontrollable current. A high electric field can also cause electrons to flow from the channel to the insulator, permanently damaging the transistor. Hence the gradual drop in supply voltage as transistors shrink.
Given that the minimum threshold voltage for turning off the transistors is 0.3 volt, dropping the supply voltage below 1 volt -- the anticipated voltage standard by the year 2005 -- will cause a greater loss in speed than can be countered by shrinking the channel length.
"Without changes in transistor structure, there will be a reduction in the performance improvement rate in a few years," warns Randy Isaac, vice president for systems technology and science at Watson. Constraints imposed by transistor design are becoming a fact of life for the computer industry. However, there are a number of ways to push even these limits back considerably.
Moving the Limits
One way to overcome the limitation on switching speed is to redesign the transistor structure using novel
materials and processes. Technologies on the horizon, such as silicon-on-insulator and double-gate transistors,
hold promise for faster processors. (See "The Next Wave of CMOS," below.) Unfortunately, all major
redesigns involve tremendous effort. "We have to ensure not only that the chips work but that they are manufacturable," says Isaac.
While none of the new structures overcome the limits related to field strength and operating voltage,
there is one way to cut voltages without compromising performance: lowering the operating temperature.
Cooling the circuits reduces the thermal energy of electrons, allowing the transistors to function at lower voltages.
There is also less scattering of electrons, resulting in higher currents and faster switching speeds.
Cooling to 50 degrees C could improve performance by at least 50 percent, while cooling to liquid-nitrogen
temperature would roughly double the speed.
If current scaling laws can be maintained, nitrogen-cooled transistors -- which might be available in about 15 years
-- would switch 10 times faster than those in use today. The actual speed of a computer could increase considerably more,
as new architectures reduce the number of times a transistor switches during a processor's clock cycle. In the past,
computer speeds have surged year by year at twice the rate of the improvement in the speed of individual transistors.
If such a trend continues, future processors might obtain clock rates as high as 30 to 40 gigahertz, 100 times as fast
as current products. But there are good reasons to believe that the pace of progress will slow down well before that
point.
Some of the factors are technical. Reliability concerns, for example, could make all tasks more difficult.
In thin-oxide layers, tunneling currents can introduce defects into the insulator, causing it to break
down and shortening the life of the transistor. To prevent that, insulating oxides will have to be made
with fewer initial defects, which act as seeds for further defects. While most researchers assume this
can be done, it could hinder progress.
Other factors are economic. For one thing, cooling systems, especially those for achieving liquid-nitrogen
temperatures, may prove expensive. For high-end computers, the cost may be outweighed by enhanced performance.
But it's not at all certain that this will be true for desktop PCs or small devices.
In fact, all the changes in lithography and transistor design will cost money, and lots of it.
"Part of the dilemma facing us is the high level of investment needed," says Isaac.
"It's probable that this will be concentrated more in development cost than in production, but it will be large nonetheless."
For the time being, the industry can afford to put ever larger sums into development, since its revenue continues
to grow by nearly 15 percent a year. But this is far faster than the growth rate of the world economy,
so it can't continue forever, either.
"Ultimately, the driver of all the technological change has to be at the demand end,"
Dennard maintains. "There have to be people out there who want more speed, more transistors, more memory."
While network servers, simulation systems and high-end graphics workstations have a nearly unlimited appetite for speed,
PC users may wonder how much benefit they will derive from faster chips.
Much depends on the emergence of a few "killer applications" that everyone will want and that will need fast processors.
Advanced voice recognition programs with natural language understanding, for instance, may require more speed
than will be available in the next few years.
Demand for such high-performance applications could spur development for years to come.
How Small Can You Get?
Taking into consideration both technical and economic issues, most experts agree that the current pace of development can continue for another five to 10 years, down to 100 nm line widths. Beyond that, growth will probably slow considerably as the ultimate limits of the CMOS technology are approached, perhaps around 50 nm line widths. Depending on improvements in computer architecture, this would mean clock rates on the order of 10 gigahertz.
Undoubtedly, a gradual deceleration in processor development will
have a large impact on the industry. For computer systems to continue improving, other avenues will have to be tried.
For example, parallel processing, an approach now limited to supercomputers, may become viable for smaller computers.
While this would require a vast reorientation by the software industry, it would perhaps enable computers to keep
improving even as individual processors face their ultimate limits.
Eric Lerner is a freelance science writer based in Lawrenceville, New
Jersey.
More Information:
How CMOS Works
Moore's Laws and Its Limits
Sharpening Lithography
The Next Wave of CMOS
Memories of Made of This
How CMOS Works
A CMOS (complementary metal-oxide semiconductor) device is formed by joining
two transistors. Each transistor, known as a MOSFET (metal-oxide semiconductor
field-effect transistor), consists of three main parts: a source, a gate and a drain,
which acts as a switch to turn on or off the current that flows between the source
and the gate. A thin layer of silicon dioxide, the gate insulator, separatesthe gate from the underlying
semiconductor channel. Dopants, small amounts of impurities,
are added to the silicon semiconductor during manufacture to create a surplus or a deficit
of electrons in the sources and drains. When no voltage is applied to the gate,
a barrier of differently doped material prevents current from flowing from source to drain.
But when a switching voltage is applied to the gate, the resulting electric field lowers
this barrier, allowing current to flow.
CMOS is "complementary" in that the voltage polarity
that causes one of the MOSFETs to turn on causes the other to turn off,
because different dopants are used to form the various regions.
Thanks to this complementary behavior, no current flows through the device
except when it switches. As a result, CMOS circuits -- unlike ordinary MOSFET circuits,
which leak current even in their "off" state -- consume little power, allowing large
numbers of them to be integrated on a chip.
Moore's Law and Its Limits
In 1965, barely six years after the integrated circuit was born,
Gordon Moore, later a cofounder of Intel Corporation, noted that the number
of transistors on a chip had doubled every year and predicted that this trend
would continue for the next decade. Ten years later, he wrote that, to his own
amazement, his prediction had been exactly fulfilled. But in the future,
he predicted, the pace of doubling would slow to once every two years.
In fact, beginning in 1975, the slope did change, to a doubling every 18 months,
or a fourfold increase every three years. This trend has become known as Moore's Law.
Moore's Law, however, has come to refer to several related trends, as well.
The driving force is the shrinkage of the dimension of transistors:
the line width -- the width of the smallest feature -- has shrunk
by a factor of two every six years. The speed, or clock rate,
of processors has doubled every two years, and the memory capacity
of DRAM (dynamic random access memory) chips has doubled every 18 months,
in step with the increase in the number of transistors on a processing chip.
Ever since Moore's Law was first promulgated,
scientists have asked the questions, When will it run out of steam?
What are the ultimate technical limits to CMOS technology? Their answers have served as an illustration
of the risks of technological prediction. For the limits confidently stated 25 years ago have
long been outstripped in the laboratory and are about to be surpassed on the production line.
The easiest way to chart the course of microcircuit development
is by the minimum feature size that can be made at a given time.
In the early 1970s, when line widths of about 10 microns were achieved,
the minimum size deemed possible for these features was 200 nanometers (nm).
Yet today's line width is 200 nm and shrinking. According to the latest estimates,
the minimum line widths achievable with good performance are around 50 nm. So, as researchers have learned
more about the possibilities of CMOS, the limits on the technology have receded. Robert Dennard, IBM Fellow
and the inventor of DRAM, observes: "It's very difficult to perceive where a limit lies, because there are
so many variables that affect the problem -- changing some of them can often remove a limit, or push it back."
Sharpening Lithography
As a slowdown in CMOS development looms on the horizon, some IBM researchers are attempting to stave it off through innovations in lithography, the technique used to define the circuits on a chip. "Currently we're approaching the limits of optical lithography," points out George Gomba, manager of lithography development at IBM's Advanced Semiconductor Technology Center in East Fishkill, New York. "We're using deep UV laser light, with a wavelength of 248 nanometers, to create line widths as narrow as 200 nm. We expect we can use it for 180 nm line widths, and perhaps 150 nm with more efficient optics."
The next step, in the view of many researchers, is to use light with a wavelength of 193 nm, which may extend line widths down to 130 nm by around 2001.
But below 130 nm, optical techniques won't work. Not only is it extremely difficult to generate shorter wavelengths, but there are almost no materials that make suitable lenses for light of such wavelengths. Fortunately, these barriers are not insurmountable.
"There are three new technologies actively being pursued to prepare for line widths below 100 nm," says Gomba. "Each is being investigated by a different company." In one approach -- extreme UV, or EUV -- a supersonic implosion of xenon gas produces radiation with a 13 nm wavelength. This approach, fostered by Intel, requires complex, multilayered mirrors to focus the radiation, because these short wavelengths cannot be focused by lenses; instead they must be reflected at glancing angles. Whether that complexity will stand in the way of success remains to be seen.
Another approach, favored by Lucent Technologies-Bell Labs, uses electrons rather than photons as the radiation. Although the technique uses projection, and is therefore faster than the traditional use of electron beams to create masks for optical lithography, it has its drawbacks. In particular, the mutual repulsion of the electrons makes it difficult, although not impossible, to achieve the energy densities and fine focusing required.
IBM is betting on an approach that it has been developing for nearly a decade: X-ray proximity lithography. This technique uses low-energy X-rays with a wavelength of only 5 nm, produced by a room-sized apparatus called a synchrotron. Because the mask is placed very near the wafer, no focusing optics are needed. But the mask must be made the same size as the final pattern. In contrast, projection techniques use a mask that is four times larger than the final pattern and therefore easier to produce.
Meanwhile, a project at IBM's Zurich Research Laboratory is following a more exploratory approach, one that eliminates the need for lenses in optical lithography. A team led by Bruno Michel has devised a technique in which a soft mask made of an organic polymer can be molded with a master pattern and then used as a kind of rubber stamp to transfer the pattern to a silicon wafer. Called a light-coupling mask, the protruding features in the patterned stamp concentrate the light in such a way that features smaller than the wavelength can be defined on the wafer.
Because it achieves high resolution without complex optics, the technique could allow lithography to be done with much simpler and cheaper equipment. It could even eliminate resists altogether, allowing reactive chemicals to be printed directly onto wafers. That would sigificantly reduce the number of processing steps, and consequently production costs. Whether or not the stamps prove suitable for full-scale manufacturing, they can be used for other applications such as making biosensors by accurately positioning biomolecules on a substrate.
Sometime around 2005, one or more of these methods will enter production. While the transition may retard progress initially, all of these techniques could theoretically be used to create 10 nm line widths. In all probability, other limits will come into play long before such dimensions are reached.
The Next Wave of CMOS
The quest for smaller transistors could lead to some major departures from conventional CMOS. The simplest new approach, under development at IBM and elsewhere, is silicon-on-insulator (SOI) -- placing a buried layer of insulating silicon dioxide under the transistors, instead of forming the transistors directly in the silicon substrate. Sitting on this oxide layer, the transistor's source and drain junctions provide less capacitance; that is, they store less charge. Accordingly, less charge is needed to switch the transistor, so the switching speed is 20 to 30 percent faster.
A more radical SOI approach is known as the ground-plane MOSFET design. Here the buried insulator, reduced to a thin layer, is underlain by a conducting ground plane. This allows the transistors to be built in a very thin silicon layer between the gate oxide and the buried oxide, reducing field distortion in very short devices.
These advantages are even greater if, instead of a ground plane, a second gate is placed under the conventional one. Such double-gate structures carry twice the current and can have a channel length shorter than that of conventional transistors. If double-gate technology can be perfected, channel lengths of 25 nanometers can be achieved with line widths of 50 nm, extending Moore's law to around 2012. While individual double gates have been fabricated at IBM -- by a team including Yuan Taur, Kevin K. Chan and Hon-Sum Philip Wong -- large-scale production may entail fundamental changes in manufacturing technology. In particular, double-gate transistors require a different layering of materials.
Memories Are Made of This
Memory chips are in for a major rethinking as they approach their lower size limits.
Because each bit stored in a chip is controlled by one transistor, memory capacities tend to expand at the same pace as the number of transistors per chip -- currently doubling every 18 months. But the basic memory storage device, the capacitor -- consisting of two charged layers separated by an insulator -- can shrink only so far. As in transistors, the insulator will eventually break down.
An alternative transistor technology, based on ferroelectrics, is able to assume two orientations, or polarization directions. By applying a voltage to the transistor, the direction of the electric field in a microscopic ferroelectric spot can be switched. "Ferroelectrics have the advantage that they don't leak, like capacitors, and so don't need to be refreshed periodically, saving a lot of additional circuitry," explains Sandip Tiwari, manager of exploratory memory and device modeling at IBM's Thomas J. Watson Research Center.
Another alternative is based on magnetism. Like ferroelectric memory, a magnetic RAM (MRAM) is nonvolatile and does not lose its charge. The principle underlying the MRAM, explains Stuart Parkin of the
Almaden Research Center, is related to that behind giant magnetoresistance (GMR), a phenomenon that Parkin helped elucidate and that is used in IBM's most advanced disk drives. Two thin layers of magnetic material are separated by a middle layer -- metallic in the case of GMR, insulating in an
MRAM. The magnetic orientation (the direction of the spin of the individual atoms) in the MRAM's two magnetic layers can be independently controlled by applying a magnetic field. The field is created by passing pulses of electric current through thin wires next to, or incorporated in, the MRAM cells. When the magnetic layers have the same orientation, a current can tunnel between them through the insulator more easily than when the orientations are different. The cell can therefore be switched between two states, representing a binary 1 and 0.
For capacitive storage, Tiwari and colleagues are developing a quantum dot memory that stores what is theoretically the smallest charge possible, a single electron. The electron's presence codes for a "1"; its absence, for a "0." The quantum dot, a trap for the electron, would be embedded in the channel of a silicon-on-insulator transistor, taking up essentially no room and allowing memory chips to shrink to the same 25 nanometer channel length that is seen as limiting transistors.
CMOS Team Members: Yuan Taur, Kevin Chan and Hon-Sum Philip Wong.
