Minimizing Inter-File Tranfers in Architectures with Separate Address Registers

In this paper, we consider instruction selection in architectures where the general-purpose register file is replaced by separate address and integer register files, each feeding a separate execution unit. In these architectures, load and store operations use address registers to compute the Iocation being accessed. Further, values in address registers can be manipulated in only a limited number of ways. In general, a value may need to be transferred from an address register to an integer register, operated on by the integer unit, and then transferred back. In this paper, we describe an optimal polynomial time algorithm to partition operations between address and integer units that minimizes the
number of interfile transfers.

By: Mayan Moudgill, Ayan Zaks

Published in: RC21884 in 2001


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