Skip to main content

Minimizing Inter-File Tranfers in Architectures with Separate Address Registers

ABSTRACT
In this paper, we consider instruction selection in architectures where the general-purpose register file is replaced by separate address and integer register files, each feeding a separate execution unit. In these architectures, load and store operations use address registers to compute the Iocation being accessed. Further, values in address registers can be manipulated in only a limited number of ways. In general, a value may need to be transferred from an address register to an integer register, operated on by the integer unit, and then transferred back. In this paper, we describe an optimal polynomial time algorithm to partition operations between address and integer units that minimizes the
number of interfile transfers.

By: Mayan Moudgill, Ayan Zaks

Published in: RC21884 in 2001

LIMITED DISTRIBUTION NOTICE:

This Research Report is available. This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. It has been issued as a Research Report for early dissemination of its contents. In view of the transfer of copyright to the outside publisher, its distribution outside of IBM prior to publication should be limited to peer communications and specific requests. After outside publication, requests should be filled only by reprints or legally obtained copies of the article (e.g., payment of royalties). I have read and understand this notice and am a member of the scientific community outside or inside of IBM seeking a single copy only.

rc21884.pdf

Questions about this service can be mailed to reports@us.ibm.com .