by W. H. Rhodes, L. A. Russell, F. E. Sakalay, R. M. Whalen
The design and performance of a newly developed magnetic core memory is described. A two-dimensional array organization and partial switching of toroidal cores were employed in the design of this low-power, high-speed memory. The memory features a unique combination of a current-steering diode matrix and a load-sharing magnetic switch for an economical and high-performance drive system. The operating memory has a storage capacity of 73,728 bits and executes instructions reliably up to a repetition rate of 1.47 mc. The discussion will include a description of the organization, the series-parallel delay line clock, the control of critical timing pulses, and the actual measured performance.
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