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IBM Journal of Research and Development  
Volume 24, Number 1, Page 15 (1980)
Programmable Logic Array (PLA) Macros
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A Heuristic Test-Pattern Generator for Programmable Logic Arrays

by E. B. Eichelberger, E. Lindbloom
This paper describes a heuristic method for generating test patterns for Programmable Logic Arrays (PLAs). Exploiting the regular structure of PLAs, both random and deterministic test-pattern generation techniques are combined to achieve coverage of crosspoint defects. Patterns to select or deselect product terms are generated through direct inspection of an array; test paths to an observable output are established by successive, rapidly converging assignments of primary input values. Results obtained with a PL/I program implementation of the method are described; these results demonstrate that the method developed is both effective and computationally inexpensive.
Related Subjects: Heuristics; LSI design automation; Programmable logic arrays (PLAs); Test-pattern generation; Testing, circuit