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An Experimental 50-Megacycle Arithmetic Unit |
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by R. M. Walker, D. E. Rosenheim, P. A. Lewis, A. G. Anderson
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An experimental 50-megacycle arithmetic unit has been built which performs a repetitive multiplication program and checks the results for errors. The unit uses pulse circuitry which has been developed to perform digital operations at a 50-megacycle pulse-repetition rate. This paper describes the arithmetic system and the circuits which perform the required functions. These circuits include a full binary adder, a phase-locked frequency divider which provides a 3.125-megacycle secondary timing source, a reshaping and retiming circuit using germanium diodes and capacitive storage, a high-speed shift register, a high-speed indicator register, and a binary word generator. Various novel features of a digital system operating at these high speeds are described. These include the use of coaxial delay lines for the distribution of signals and as storage elements, and the use of secondary emission tubes in amplifier and multivibrator circuits. In a 50-megacycle system the interdependence of the space and time dimensions is marked, and although this introduces problems which are not ordinarily encountered in computing systems, it may be used advantageously to provide features such as the variable-phase clock system used in the arithmetic unit. The performance and reliability of the arithmetic unit are discussed as well as the reliability of the components and circuits which make up the system. Although the techniques and circuitry discussed here have been applied only to a relatively simple arithmetic unit, it is felt that they could be useful in a variety of high-speed computing and measurements applications. |
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| Related Subjects: Arithmetic and logical unit design; Clocking |
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