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IBM Journal of Research and Development  
Volume 40, Number 4, Page 475 (1996)
IBM ASIC design and testing
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IC technology and ASIC design for the Cray J90 supercomputer

by D. J. Poli, M. S. Berry, J. N. Kruchowski
The decision to use ASIC technology over a full- or semi-custom approach in the design of a computer system is influenced by many factors, and has a significant impact on the design methodology as well as on the completion schedule of the product. The Cray Research J90™ line of 100-MHz supercomputer systems is an example of a system whose performance, cost, and schedule needs drove the designers to an ASIC solution. The J90 comprises varying numbers of ten unique ASICs, each designed in a 0.5-μm CMOS technology. The largest of the ASICs contains more than 500,000 equivalent two-way NAND CMOS gates. The design cycle, including integrated circuit and first-level packaging technology selection, took just over two years from concept to production. This paper presents a brief history of the Cray ELS (Entry-Level Systems) division and discusses some of the decision processes and trade-offs made during the design of the J90 system, including the decision to use ASIC technology, and its effect on the overall design methodology and CAD flow. The design methodology, which utilized a ground-rule-based HDL/synthesis approach, and the physical design of the chips, which made use of industry-standard and vendor-proprietary tools, are discussed. Finally, conclusions as to the applicability and the success of utilizing an "off-the-shelf" ASIC technology are drawn.
Related Subjects: ASICs; Circuit and device technology; CMOS; Design automation; Design verification; Integrated circuit design; LSI design automation; LSSD design and testing; Microelectronics; VLSI