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Related Papers
2003
Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies
2000
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Modular nets (MNETS): A modular design methodology for computer timers
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BooleDozer: Logic synthesis for ASICs
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Circuit placement, chip optimization, and wire routing for IBM IC technology
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Design considerations for Digital's PowerStorm graphics processor
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Design methodology for IBM ASIC products
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Design planning for high-performance ASICs
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IC technology and ASIC design for the Cray J90 supercomputer
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PowerPC AS A10 64-bit RISC microprocessor
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Technology-migratable ASIC library design
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Test methodologies and design automation for IBM ASICs
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The past and present roles of computer-aided engineering in DASD design
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Parallel algorithms for chip placement by simulated annealing
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ACORN: A system for CVS macro design by tree placement and tree customization
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An iterative-improvement penalty-function-driven wire routing system
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Automated technology mapping
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Constraint solver for generalized IC layout
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Custom Chip/Card Design System
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1984
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Statistical failure analysis of system timing
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Using a hardware simulation engine for custom MOS structured designs
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OYSTER: A Study of Integrated Circuits as Three-Dimensional Structures
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A Bipolar VLSI Custom Macro Physical Design Verification Strategy
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A VLSI Design Verification Strategy
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Bipolar Chip Design for a VLSI Microprocessor
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Boolean Comparison of Hardware and Flowcharts
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Design Verification System for Large-Scale LSI Designs
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Electrical Design of a High Speed Computer Package
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Timing Analysis of Computer Hardware
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Design Automation in IBM
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Fleshing Out Projections
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GRIN: Interactive Graphics for Modeling Solids
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Logic Synthesis Through Local Transformations
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Number of Vias: A Control Parameter for Global Wiring of High-Density Chips
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Stand-Alone Wiring Program for Josephson Logic
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Solid Logic Design Automation
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