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Related Papers
2007
IBM POWER6 microprocessor physical design and design methodology
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Decomposing the load–store queue by function for power reduction and scalability
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CMOS design near the limit of scaling
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Early analysis tools for system-on-a-chip design
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SOI technology for the GHz era
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Architecture and software support in IBM S/390 Parallel Enterprise Servers for IEEE Floating-Point arithmetic
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Evaluation of branch-prediction methods on traces from commercial applications
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S/390 CMOS Cryptographic Coprocessor Architecture: Overview and design considerations
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S/390 Parallel Enterprise Server CMOS Cryptographic Coprocessor
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The S/390 G5 floating-point unit
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Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors
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The floating-point unit of the PowerPC 603e microprocessor
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Overview of gate linewidth control in the manufacture of CMOS logic chips
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POWER2 fixed-point, data cache, and storage control units
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SCISM: A scalable compound instruction set machine
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Proof of correctness of high-performance 3-1 interlock collapsing ALUs
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On-the-fly decoder for multiple byte errors
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Signal processor chip implementation
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Iterative Exhaustive Pattern Generation for Logic Testing
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Exclusive-OR Representations of Boolean Functions
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Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test
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Design Considerations for a VLSI Microprocessor
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IBM 3081 Processor Unit: Design Considerations and Design Process
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Lead Reduction Among Combinatorial Logic Circuits
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System Development and Technology Aspects of the IBM 3081 Processor Complex
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Logic Synthesis Through Local Transformations
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On Measures of Logic Performance: Logic Quantum, Factor, and Figure of Merit
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PERT as an Aid to Logic Design
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The Multipurpose Bias DevicePart II: The Efficiency of Logical Elements
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