2005 | Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements |
2002 | Challenges and future directions for the scaling of dynamic random-access memory (DRAM) |
2002 | CMOS design near the limit of scaling |
2002 | Effect of increasing chip density on the evolution of computer architectures |
2002 | Infrastructure requirements for a large-scale, multi-site VLSI development project |
2002 | Maintaining the benefits of CMOS scaling when scaling bogs down |
2002 | SOI technology for the GHz era |
2002 | Why BiCMOS and SOI BiCMOS? |
1998 | Integrating the MPEG-2 subsystem for digital television |
1996 | BooleDozer: Logic synthesis for ASICs |
1996 | Circuit placement, chip optimization, and wire routing for IBM IC technology |
1996 | Design considerations for Digital's PowerStorm graphics processor |
1996 | Design methodology for IBM ASIC products |
1996 | Design planning for high-performance ASICs |
1996 | IC technology and ASIC design for the Cray J90 supercomputer |
1996 | PowerPC AS A10 64-bit RISC microprocessor |
1996 | Technology-migratable ASIC library design |
1996 | Test methodologies and design automation for IBM ASICs |
1996 | The floating-point unit of the PowerPC 603e microprocessor |
1995 | A 64Kb × 32 DRAM for graphics applications |
1995 | A low-noise TTL-compatible CMOS off-chip driver circuit |
1995 | CMOS circuits for Gb/s serial data communication |
1995 | CMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications |
1995 | CMOS scaling into the 21st century: 0.1 μm and beyond |
1995 | Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications |
1995 | Design at the system level with VLSI CMOS |
1995 | Digital delay line clock shapers and multipliers |
1995 | High-level synthesis in an industrial environment |
1995 | Interconnect design with VLSI CMOS |
1995 | Multipurpose DRAM architecture for optimal power, performance, and product flexibility |
1995 | Overview of gate linewidth control in the manufacture of CMOS logic chips |
1995 | Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier |
1995 | Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor |
1995 | The evolution of IBM CMOS DRAM technology |
1995 | VerityA formal verification program for custom CMOS circuits |
1995 | VLSI on-chip interconnection performance simulations and measurements |
1992 | A single-chip IBM System/390 floating-point processor in CMOS |
1991 | A 128Kb CMOS static random-access memory |
1991 | IBM Enterprise System/9000 Type 9121 Model 320 air-cooled processor technology |
1991 | Visualization in a VLSI design automation system |
1991 | Waveform-relaxation-based circuit simulation on the Victor V256 parallel processor |
1990 | Boundary-scan design principles for efficient LSSD ASIC testing |
1990 | Built-in self-test support in the IBM Engineering Design System |
1990 | Design for testability and diagnosis in a VLSI CMOS System/370 processor |
1990 | High-speed signal propagation on lossy transmission lines |
1990 | On-chip wiring for VLSI: Status and directions |
1990 | The development of ultra-high-frequency VLSI device test systems |
1989 | Architecture, design, and operating characteristics of a 12-ns CMOS functional cache chip |
1988 | A multi-purpose VLSI chip for adaptive data compression of bilevel images |
1987 | Contact metallurgy development for VLSI logic |
1987 | Electrical and microstructural investigation of polysilicon emitter contacts for high-performance bipolar VLSI |
1987 | Signal degradation through module pins in VLSI packaging |
1985 | VLSI wiring capacitance |
1984 | An interactive system for VLSI chip physical design |
1984 | KWIRE: A multiple-technology, user-reconfigurable wiring tool for VLSI |
1983 | A ''Zero-Time'' VLSI Sorter |
1982 | A Bipolar VLSI Custom Macro Physical Design Verification Strategy |
1982 | A VLSI Bipolar Metallization Design with Three-Level Wiring and Area Array Solder Connections |
1982 | A VLSI Design Verification Strategy |
1982 | Bipolar Chip Design for a VLSI Microprocessor |
1982 | Design Considerations for a VLSI Microprocessor |
1982 | Evolution and Accomplishments of VLSI Yield Management at IBM |
1981 | Bipolar Circuit Design for a 5000-Circuit VLSI Gate Array |
1981 | Techniques for Improving Engineering Productivity of VLSI Designs |
1980 | Reduction of Leakage by Implantation Gettering in VLSI Circuits |
1980 | VLSI Device Phenomena in Dynamic Memory and Their Application to Technology Development and Device Design |
1980 | Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product |