IBM Journal of Research and Development
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IBM Journal of Research and Development

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Show details for IBM Journal of Research and Development - Volume 52 (2008)IBM Journal of Research and Development - Volume 52 (2008)
Show details for IBM Journal of Research and Development - Volume 51 (2007)IBM Journal of Research and Development - Volume 51 (2007)
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Hide details for Issue 1/2Issue 1/2
Page 3Preface by D. J. Fleming
Page 5Design at the system level with VLSI CMOS by R. F. Sechler, G. F. Grohoski
Page 23Interconnect design with VLSI CMOS by R. F. Sechler
Page 33Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor by K. Bernstein, J. E. Bertsch, L. G. Heller, E. J. Nowak, F. R. White
Page 43A 64Kb × 32 DRAM for graphics applications by T. Sunaga, K. Hosokawa, S. H. Dhong, K. Kitamura
Page 51Multipurpose DRAM architecture for optimal power, performance, and product flexibility by W. F. Ellis, J. E. Barth,Jr., S. Divakaruni, J. H. Dreibelbis, A. Furman, E. L. Hedberg, H. S. Lee, T. M. Maffitt, C. P. Miller, C. H. Stapper, H. L. Kalter
Page 63Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier by D. M. Kuchta, H. A. Ainspan, F. J. Canora, R. P. Schneider,Jr.
Page 73CMOS circuits for Gb/s serial data communication by J. F. Ewen, M. Soyuer, A. X. Widmer, K. R. Wrenner, B. D. Parker, H. A. Ainspan
Page 83Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications by H. J. Shin, D. J. Pearson, S. K. Reynolds, A. C. Megdanis, S. Gowda, K. R. Wrenner
Page 93Digital delay line clock shapers and multipliers by R. A. Bechade, R. M. Houle
Page 105A low-noise TTL-compatible CMOS off-chip driver circuit by S. H. Dhong, M. Tanaka, S. W. Tomashot, T. Kirihata
Page 113Architectural timing verification of CMOS RISC processors by P. Bose, S. Surya
Page 131High-level synthesis in an industrial environment by R. A. Bergamaschi, R. A. O'Connor, L. Stok, M. Z. Moricz, S. Prakash, A. Kuehlmann, D. S. Rao
Page 149Verity—A formal verification program for custom CMOS circuits by A. Kuehlmann, A. Srinivasan, D. P. LaPotin
Page 167The evolution of IBM CMOS DRAM technology by E. Adler, J. K. DeBrosse, S. F. Geissler, S. J. Holmes, M. D. Jaffe, J. B. Johnson, C. W. Koburger,III, J. B. Lasky, B. Lloyd, G. L. Miles, J. S. Nakos, W. P. Noble,Jr., S. H. Voldman, M. Armacost, R. Ferguson
Page 189Overview of gate linewidth control in the manufacture of CMOS logic chips by D. G. Chesebro, J. W. Adkisson, L. R. Clark, S. N. Eslinger, M. A. Faucher, S. J. Holmes, R. P. Mallette, E. J. Nowak, E. W. Sengle, S. H. Voldman, T. W. Weeks
Page 201Integrated cost and productivity learning in CMOS semiconductor manufacturing by G. A. Leonovich, A. P. Franchino, W. J. Miller, U. E. Tsou
Page 215A half-micron CMOS logic generation by C. W. Koburger,III, W. F. Clark, J. W. Adkisson, E. Adler, P. E. Bakeman, A. S. Bergendahl, A. B. Botula, W. Chang, B. Davari, J. H. Givens, H. H. Hansen, S. J. Holmes, D. V. Horak, C. H. Lam, J. B. Lasky, S. E. Luce, R. W. Mann, G. L. Miles, J. S. Nakos, E. J. Nowak, G. Shahidi, Y. Taur, F. R. White, M. R. Wordeman
Page 229CMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications by G. G. Shahidi, J. D. Warnock, J. Comfort, S. Fischer, P. A. McFarland, A. Acovic, T. I. Chappell, B. A. Chappell, T. H. Ning, C. J. Anderson, R. H. Dennard, J. Y. Sun, M. R. Polcari, B. Davari
Page 245CMOS scaling into the 21st century: 0.1 μm and beyond by Y. Taur, Y. J. Mii, D. J. Frank, H. S. Wong, D. A. Buchanan, S. J. Wind, S. A. Rishton, G. A. Sai-Halasz, E. J. Nowak
Page 261Recent publications by IBM authors
Page 275Recent IBM patents
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Show details for IBM Journal of Research and Development - Volume 38 (1994)IBM Journal of Research and Development - Volume 38 (1994)
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