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IBM Journal of Research and Development  
Volume 31, Number 1, Page 120 (1987)
Office Automation Technologies
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Path hierarchies in interconnection networks

by P. A. Franaszek
This paper treats the problem of latency minimization in an interconnection network for a system of N high-performance devices. The networks considered here have data transport separated from control, with the data subnetwork designed so that each network function requires only a single control message, and thus only one contention-resolution delay. For sufficiently large N it is shown that (for an abstract hardware model) minimizing contention delays requires that each message subject to such delays have more than one way of reaching its destination (e.g., via a path hierarchy). The overall approach is discussed in the context of the processor-memory interconnection problem in parallel computing.
Related Subjects: Computer architecture; Networks; Parallel processing