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IBM Journal of Research and Development  
Volume 25, Number 2/3, Page 126 (1981)
VLSI Circuit Design
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A 1024-Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell

by J. A. Dorler, J. M. Mosley, G. A. Ritter, R. O. Seeger, J. R. Struk
This paper presents the design of a 1K-byte random access memory using a cross-coupled complementary transistor switch (CTS) cell. The memory operates with a 4.25-V power supply and achieves a 15-ns access time with a power dissipation of 1.8 W. This paper also demonstrates the advantages of using the CTS cell to achieve high circuit density and good performance of memory arrays. Array attributes, cell selection criteria, and cell operation (both ideal and in situ) as well as design considerations are covered. Hardware performance is also briefly summarized.
Related Subjects: Integrated circuit design; LSI; Memory (computer) design and technology; Memory, random-access